Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 227

Powerquicc family

Table of Contents

Table 7-12. Copyback Buffer Select Field (DC_ADR[20–27]) Encoding

DC_ADR[20–27]

DC_CST Commands

All DC_CST commands, except the load-and-lock cache block and flush cache block commands, are

executed immediately after writing to the DC_CST register and do not generate any errors. Therefore,

there is no need to check the error type bits in the DC_CST register except when executing the

load-and-lock cache block and flush cache block commands.

Note that when the data cache is executing a command, it stops handling CPU requests, which can result

in machine stalls.

Data Cache Enable/Disable Commands

The data cache enable command (DC_CST[CMD] = 0b0010) is used to enable the data cache; the data

cache disable command (DC_CST[CMD] = 0b0100) is used to disable the data cache. Neither of these

commands has any error cases. The current state of the data cache is available by reading the data cache

enable status bit (DC_CST[DEN]).

When disabled, the MPC885 ignores the data cache state bits and operates as if all accesses have

caching-inhibited access attributes (that is, all accesses are propagated to the bus as single-beat

transactions). Disabling the data cache does not affect the data address translation logic; MSR[DR]

controls data address translation.

Note that the data cache is disabled at hard reset. Also, the data cache is automatically disabled when a

type 1 data cache error (see

Data Cache Load-and-Lock Cache Block Command

The data cache load-and-lock cache block command (DC_CST[CMD] = 0b0110) is used to lock critical

data in the data cache. Locked cache blocks are not replaced during misses and are not affected by

invalidate commands.

To load and lock one or more cache blocks:

1. Read the DC_CST error type bits to clear them.

2. Write the address of the cache block to be locked to the DC_ADR register.

3. Write the load-and-lock cache block command (DC_CST[CMD] = 0b0110) to the DC_CST

Freescale Semiconductor

Copyback buffer data word 0

Copyback buffer data word 1

Copyback buffer data word 2

Copyback buffer data word 3

Copyback address

for DC_CST[CCER1] conditions) generates a machine check

MPC885 PowerQUICC Family Reference Manual, Rev. 2

Buffer Selected

Instruction and Data Caches