Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 679

22.8 Multidrop Systems and Address Recognition
In multidrop systems, more than two stations can be on a network, each with a specific address.
Figure 22-2 shows two examples of this configuration. Frames made up of many characters can be
broadcast as long as the first character is the destination address. The UART frame is extended by one bit
to distinguish an address character from standard data characters. Programmed in PSMR[UM], the
controller supports the following two multidrop modes:
Automatic multidrop mode—The controller checks the incoming address character and accepts
subsequent data only if the address matches one of two user-defined values. The two 16-bit address
registers, UADDR1 and UADDR2, support address recognition. Only the lower 8 bits are used so the
upper 8 bits should be cleared; for addresses less than 8 bits, unused high-order bits should also be cleared.
The incoming address is checked against UADDR1 and UADDR2. When a match occurs, RxBD[AM]
indicates whether UADDR1 or UADDR2 matched.
• Manual multidrop mode—The controller receives all characters. An address character is always
written to a new buffer and can be followed by data characters. User software performs the address
comparison.
1
Tx
MASTER
Tx
Two 8-Bit Addresses can be Automatically
Recognized in Either Configuration
22.9 Receiving Control Characters
The UART receiver can recognize special control characters used in a message-based environment. Eight
control characters can be defined in a control character table in the UART parameter RAM. Each incoming
character is compared to the table entries using a mask (the received control character mask, RCCM) to
strip don't cares. If a match occurs, the received control character can either be written to the receive buffer
or rejected.
Freescale Semiconductor
2
Rx Tx Rx
SLAVE 1
Rx Tx Rx
UADDR1
UADDR2
Figure 22-2. Two UART Multidrop Configurations
MPC885 PowerQUICC Family Reference Manual, Rev. 2
3 4
Tx Rx Tx Rx
SLAVE 2 SLAVE 3
Tx Rx Tx Rx
PAODR
Choose Wired-Or Operation in the Port A
Open-Drain Register to Allow Multiple Transmit
Pins to be Directly Connected
SCC UART Mode
+ V
R
+ V
R
22-7