Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 637

Powerquicc family

Table of Contents

12. SISTR and SIRP do not need to be read, but can be used for debugging once the channels are

13. Enable SCC3 for HDLC operation (to handle the LAPD protocol of the D channel), and configure

SCC2 and SMC2 as needed.

GCI Bus Implementation

The MPC885 fully supports both the normal mode (also known as ISDN-oriented modular rev 2.2

(IOM-2)) and the SCIT mode of the general circuit interface (GCI). It also supports the D channel access

control in S/T interface terminals by using the command/indication (C/I) channel.

The GCI bus consists of four signals—two data lines, a clock, and a frame synchronization line. Usually,

an 8-KHz frame structure defines the various channels within the 256 Kbps data rate. The MPC885

supports two independent GCI buses, each with independent receive and transmit sections. With a data rate

of 2,048 Kbps, the interface can also be used in a multiplexed frame structure on which up to eight physical

layer devices multiplex their GCI channels.

In the GCI bus, the clock rate is twice the data rate. The SI divides the input clock by two to produce the

data clock. The MPC885 also has data strobe lines and the 1× data rate clock L1CLKOx outputs used as

an interface for devices that do not support the GCI bus. Shown in

Tx and Rx channel are as follows:

L1RSYNCx—Used as a GCI sync signal. Input to the MPC885. The clock periods following the

sync pulse designate the GCI frame.

L1RCLKx—Used as a GCI clock. Input to the MPC885. The L1RCLKx signal is twice the data

L1RXDx—Used as a GCI receive data. Input to the MPC885.

L1TXDx—Used as a GCI transmit data. Open-drain output. Driven only for the bits that are

programmed in the SI RAM. Otherwise, it is three-stated.

L1CLKOx—Optional signal; Output. For clock devices that do not interface directly to the GCI. It

is 1× output of L1RCLKx.; otherwise, if the double-speed clock is used (SIMODE[DSCx] is set),

it is L1RCLKx divided by 2.

(2X the Data Rate)

Notes: Clock is not to scale.

L1CLKO is not shown.

Freescale Semiconductor

Figure 20-27. GCI Bus Signals

MPC885 PowerQUICC Family Reference Manual, Rev. 2

20-27, the GCI signals for each

Serial Interface