Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 950

Powerquicc family

Table of Contents

CPM Interrupt Controller

Source Description

Parallel I/O—PC14

Parallel I/O—PC13

Parallel I/O—PC12

SDMA channel bus error

RISC timer table

The table is the same as the CPM interrupt priority table

vector numbers are fixed. and are not affected by the ability to re-prioritize the USB and SCCs described

Section 35.5.2, "CPM Interrupt Pending Register (CIPR)."

vector, which the CPM issues if it requested an interrupt that the user cleared before the core serviced it

and no other interrupts for the CPM are pending. The user should provide an error interrupt service routine

even if it is only an rfi instruction.

CPIC Registers

There are four CPIC registers:

CPM interrupt configuration register (CICR)—Defines CPM interrupt attributes.

CPM interrupt pending register (CIPR)—Indicates which CPM interrupt sources require interrupt

CPM interrupt mask register (CIMR)—Can be used to mask CPM interrupt sources.

CPM interrupt in-service register (CISR)—Allows nesting interrupt requests within the CPM

interrupt level.

Note that the names and placement of bits is identical in the CIPR, CIMR, and CISR.

CPM Interrupt Configuration Register (CICR)

The CPM interrupt configuration register (CICR) defines CPM interrupt request levels, the priority

between the USB and SCCs, and the highest priority interrupt.

Table 35-2. Interrupt Vector Encodings (continued)

MPC885 PowerQUICC Family Reference Manual, Rev. 2

Source Description

Parallel I/O—PC8

Parallel I/O—PC7

Parallel I/O—PC6

Parallel I/O—PC5

Parallel I/O—PC4

35-1) except that the USB and 3 SCC

Also the last entry in this table is the error

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