Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 717

23.14.5 Using the Time-Slot Assigner (TSA)
HDLC bus controllers can be used with a time-division multiplexed transmission line and a local bus, as
shown in Figure 23-16. Local stations use time slots to communicate over the TDM transmission line;
stations that share a time slot use the HDLC bus protocol to control access to the local bus.
Rx
Tx
Line Driver
NOTES:
1. All TXD pins of slave devices should be configured to open-drain in the port C parallel I/O port.
2. The TSA in the SI of each station is used to configure the preferred time slot.
3. The choice of the number of stations to share a time slot is user-defined. It is two in this example.
Figure 23-16. HDLC Bus TDM Transmission Line Configuration
The local SCCs in HDLC bus mode communicate only with the transmission line and not with each other.
The SCCs use the TSA of the serial interface, receiving and sending data over L1TXDx and L1RXDx.
Because collisions are still detected from the individual SCC CTS pin, it must be configured in port C to
connect to the chosen SCC. Because the SCC only receives clocks during its time slot, CTS is sampled
only during the Tx clock edges of the particular SCC time slot.
23.14.6 HDLC Bus Protocol Programming
The HDLC bus is implemented using the SCC in HDLC mode with bus-specific options selected in the
PSMR and GSMR, as outlined below. See also
23.14.6.1 Programming GSMR and PSMR for the HDLC Bus Protocol
To program the protocol-specific mode register (PSMR), set the bits as described below:
• Configure NOF as preferred
• Set RTE and BUS to 1
• Set BRM to 1 if delayed RTS is desired
• Configure CRC to 16-bit CRC CCITT (0b00).
• Configure other bits to zero or default.
Freescale Semiconductor
L1 L1
L1RXD TXD CTS L1RXD
HDLC Bus HDLC Bus
Controller Controller
A
Stations share time-slot n
Section 23.5, "Programming the SCC HDLC Controller."
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Local HDLC Bus
L1
TXD CTS L1RXD TXD CTS
HDLC Bus
Controller
B C
Stations share time-slot m
SCC HDLC Mode
+ 5 V
R
L1
L1RXD TXD CTS
HDLC Bus
Controller
D
23-21