Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 129

Table 2-1. MPC885 Internal Memory Map (IMMR[14–15]=00) (continued)
Offset
A9A SMCM2—SMC2 mask register
A9B–A9F Reserved
AA0 SPMODE—SPI mode register
AA2–AA5 Reserved
AA6 SPIE—SPI event register
AA7–AA9 Reserved
AAA SPIM—SPI mask register
AAB–AAC Reserved
AAD SPCOM—SPI command register
AAE–AB1 Reserved
AB2 PIPC—PIP configuration register
AB4–AB5 Reserved
AB6 PTPR—PIP timing parameters register
AB8 PBDIR—Port B data direction register
ABC PBPAR—Port B pin assignment register
AC0 PBODR—Port B open drain register
AC4 PBDAT—Port B data register
AC8 PEDIR — Port E data direction register
ACC PEPAR — Port E data assignment register
ADO PESO — Port E special options
AD4 PEODR — Port E open drain register
AD8 PEDAT — Port E data register
Communications Processor Timing Register - Contains RMII Timing for the FECs
ADC CPTR — CPTR Register
Freescale Semiconductor
Name
Serial Peripheral Interface (SPI)
Parallel Interface Port (PIP) and Port B
Port B Registers
Port E Registers
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Size Section/Page
8 bits 29.3.12/29-18
29.4.11/29-29
29.5.9/29-35
5 bytes —
16 bits 30.4.1/30-6
4 bytes —
8 bits 30.4.2/30-8
3 bytes —
8 bits 30.4.2/30-8
2 bytes —
8 bits 30.4.3/30-9
4 bytes —
16 bits 33.4.1/33-8
2 bytes —
16 bits 33.4.4/33-10
32 bits 34.3.1.3/34-10
32 bits 34.3.1.4/34-11
32 bits 34.3.1.1/34-9
32 bits 34.3.1.2/34-9
32 bits 34.6.1.3/34-23
32 bits 34.6.1.4/34-24
32 bits 34.6.2/34-25
32 bits 34.6.1.1/34-22
32 bits 34.5.1.1/34-18
32 bits 45.3.1/45-11,
52.1/52-1
Memory Map
(UART)
(Transparent)
(GCI)
2-11