Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 319

The following sections describe the events that can initiate an internal assertion of HRESET and SRESET.
11.1.3.1 Software Watchdog Reset
When the core watchdog counter decrements to zero, a software watchdog reset is asserted generating an
internal hard reset sequence. Note that this is the default response; that is, an NMI to the core can be issued
instead of a hard reset, and the timer can be disabled. See
11.1.3.2 Checkstop Reset
If the core enters a checkstop state and PLPRCR[CSR] = 1, the checkstop reset is asserted generating an
internal hard reset sequence. See
11.1.4 Debug Port Hard or Soft Reset
When the development port receives a hard or soft reset request from a development tool, an internal hard
or soft reset sequence is generated. The development tool must reconfigure the debug port following a reset
event. See Section 53.3.2.1.2, "Development Serial Data In (DSDI)."
11.1.5 JTAG Reset
When the JTAG logic asserts the JTAG reset signal, an internal soft reset sequence is generated.
11.1.6 Power-On and Hard Reset Sequence
Figure 11-1 shows the reset sequence following a power-on or internal or external hard reset event.
Internal or External
HRESET Asserted
External HRESET
Asserted
Freescale Semiconductor
Section 14.6.2, "PLL and Reset Control Register (PLPRCR)."
Power-On
Power On
Reset
PORESET is Negated and PLL Lock
Internally
Initiated
HRESET
Timer Expires (After 512 Clocks)
Wait
16 Clocks Expire
Start Normal Operation
(From system reset interrupt exception vector)
Figure 11-1. Power-On and Hard Reset Sequence
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Section 10.7, "Software Watchdog Timer."
• Sample MODCK pins and initialize clocks
• HRESET and SRESET are asserted
• HRESET and SRESET assert
• The time counter is set to 512
• Sample configuration from data pins
• Negate HRESET and SRESET
• Wait for 16 clocks
• Test for HRESET or SRESET
Reset
11-3