Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 246

Memory Management Unit
Figure 8-1 shows the flow for a read access or instruction fetch.
Data/Instruction Fetch
(Fast TLB Hit)
Compare address
TLB reload (read page
description from external
memory to TLB)
Figure 8-2 shows the flow for a load/store access, assuming translation is enabled. Because data transfers
have less locality than instruction fetches, the DMMU does not implement a fast TLB mechanism. The
DTLB is accessed for each transfer simultaneously with the data cache tag read, hence there is no time
penalty.
8-4
32-bit EA is generated
Same Page
Yes
Use current page description
?
No
with TLB (1 clock penalty)
entries
TLB
Yes
Hit
?
No
(20–23 clock penalty
@ one wait-state
external memory)
Use page description from TLB
Figure 8-1. Read/Instruction Fetch Flow Diagram
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Is page
No
valid
?
Yes
Access permitted
No
by page protection
?
Yes
TLB Error Exception
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