Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 831

Powerquicc family

Table of Contents

Serial Peripheral Interface (SPI)

The serial peripheral interface (SPI) allows the MPC885 to exchange data between other MPC885 chips,

the MC68360, the MC68302, the M68HC11 and M68HC05 microcontroller families, and peripheral

devices such as EEPROMs, real-time clocks, A/D converters, and ISDN devices.

The SPI is a full-duplex, synchronous, character-oriented channel that supports a four-wire interface

(receive, transmit, clock and slave select). The SPI block consists of transmitter and receiver sections, an

independent baud rate generator, and a control unit. The transmitter and receiver sections use the same

clock, which is derived from the SPI baud rate generator in master mode and generated externally in slave

mode. During an SPI transfer, data is sent and received simultaneously.

Because the SPI receiver and transmitter are double-buffered, as shown in

size (latency) is 2 characters. The SPI's msb is shifted out first. When the SPI is disabled in the SPI mode

SPI Mode Register

The following is a list of the SPI's main features:

Four-signal interface (SPIMOSI, SPIMISO, SPICLK, and SPISEL)

Full-duplex operation

Works with data characters from 4 to 16 bits long

Supports back-to-back character transmission and reception

Freescale Semiconductor

Transmit_Register

Pins Interface

Figure 30-1. SPI Block Diagram

MPC885 PowerQUICC Family Reference Manual, Rev. 2

Peripheral Bus

Receive_Register

Shift_Register

30-1, the effective FIFO