Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 621

20.2.3.8 SI RAM Programming Example
This section shows how to program the SI RAM to support the 10-bit IDL bus whose format is shown in
Figure 20-26. Here, the TSA supports the B1 channel with SCC2, the D channel with SCC3, the first 4 bits
of the B2 channel with an external device (using a strobe to enable the external device), and the last 4 bits
of B2 with SMC1. Additionally, the TSA marks the D channel with another strobe signal.
Partition the frame from the beginning (the sync) to the end according to the support needed:
• 8 bits (B1)—SCC2
• 1 bit (D)—SCC3 + strobe1
• 1 bit—No support
• 4 bits (B2)—strobe2
• 4 bits (B2)—SMC1
• 1 bit (D)—SCC3 + strobe1
Each partition represents one SI RAM entry.
Table 20-3. Example SI RAM Entry Settings for an IDL Bus
Entry
Number
SWTR
1 0
2 0
3 0
4 0
5 0
6 0
Because the IDL requires the same routing for both receiving and sending, the above entries should be
written to both the Rx and Tx route RAM. Set SIMODE[CRTx] (common receive/transmit) to instruct the
TSA to use the same clock and sync for both sets of SI RAM entries.
For examples showing register programming, see
Section 20.2.6.3, "GCI Interface (SCIT Mode) Programming Example."
20.2.4 The SI Registers
The following sections describe the SI registers.
20.2.4.1 SI Global Mode Register (SIGMR)
The SI global mode register (SIGMR), shown in
enables the individual TDM channels.
Freescale Semiconductor
Table 20-3
SSEL CSEL CNT
0000 010 0000
0001 011 0000
0000 000 0000
0010 000 0011
0000 101 0011
0001 011 0000
Section 20.2.5.2, "Programming the IDL Interface,"
Figure
MPC885 PowerQUICC Family Reference Manual, Rev. 2
shows the SI RAM entries.
SI RAM
BYT LST
1 0 8 bits SCC2 (B1)
0 0 1 bit SCC3 strobe1 (D)
0 0
0 0 4 bits strobe2 (B2)
0 0 4 bits SMC1 (B2)
0 1 1 bit SCC3 strobe1
20-12, defines the SI RAM division modes and
Serial Interface
Description
1 bit no support
and
20-15