Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 296

System Interface Unit
Table 10-4 describes SYPCR fields.
Bits Name
0–15 SWTC Software watchdog timer count. Count value for the software watchdog timer.
16–23 BMT Bus monitor timing. Defines the timeout period, in 8 system clock resolution, for the bus monitor.
maximum timeout is 2,040 clocks.
24 BME Bus monitor enable. Controls bus monitor operation during internal-to-external bus cycles.
0 Disable the bus monitor
1 Enable the bus monitor
Note: If the bus monitor is disabled, transfer error conditions do not cause TEA to be asserted.
25–27 — Reserved, should be cleared.
28 SWF Software watchdog freeze
0 The software watchdog timer continues counting even if FRZ is asserted.
1 The software watchdog timer stops counting when FRZ is asserted.
29 SWE Software watchdog enable.
To disable the software watchdog timer, it should be cleared by the software after a system reset.
0 Software watchdog timer disabled
1 Software watchdog timer enabled (default)
30 SWRI Software watchdog reset/interrupt select.
0 The software watchdog timer causes an NMI (system reset interrupt) to the core.
1 The software watchdog timer causes an HRESET. (default)
31 SWP Software watchdog prescale.
0 The software watchdog timer is not prescaled.
1 The software watchdog timer is prescaled by a factor of 2,048 (default).
10.4.4 Transfer Error Status Register (TESR)
The transfer error status register (TESR) has a bit for each transfer error exception source. Set bits indicate
what type of transfer error exception that occurred since bits were last cleared. Bits are cleared by reset or
by writing ones to them. Canceled speculative accesses that do not cause an interrupt may set these bits.
TESR has two identical sets of fields, one for instruction transfers and one for data transfers.This register
is affected by HRESET and SRESET.
10-8
Table 10-4. SYPCR Field Descriptions
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Description
Freescale Semiconductor