Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 159

Chapter 4
MPC8xx Core Register Set
This chapter describes the software-accessible registers implemented on the MPC885. These include
registers that are defined by the PowerPC architecture and registers that are specific to the MPC885. This
section does not include registers that are part of the communication processor module (CPM); those
registers are described in Part V, "Communications Processor Module." Refer to the Programming
Environments Manual for 32-Bit Implementations of the PowerPC Architecture for more information
about the architecture's register definition.
4.1 MPC885 Register Implementation
Registers implemented in the MPC885 core can be grouped as follows:
• Two types of registers are defined by the PowerPC architecture.
— User registers, which can be accessed by user-level software. All PowerPC user-level registers
are defined by the user instruction set architecture (UISA), except for the time base registers,
which can be read by user-level software and are defined by the virtual environment
architecture (VEA). User registers are described in
Registers."
— Supervisor registers, which can be accessed by supervisor software and in some cases are the
automatic result of hardware activity, such as when an exception is taken and when the system
is reset. All supervisor registers are defined by the operating environment architecture (OEA),
except the time base registers, which can be written to only by supervisor software and are
defined by the VEA. PowerPC supervisor registers are described in
Registers—Supervisor Registers."
The UISA, VEA, and OEA architecture definitions are described in
PowerPC Architecture."
• MPC885-specific registers. These registers are either supervisor-level registers or debug registers.
These are described briefly in
provide cross references to the sections in this book where each register is described.
4.1.1 PowerPC Registers—User Registers
The MPC885 implements the user-level registers defined by the PowerPC architecture except those
required for supporting floating-point operations (the floating-point register file (FPRs) and the
floating-point status and control register (FPSCR)). User-level PowerPC registers are listed in
and Table 4-2. Table 4-2
Freescale Semiconductor
Section 4.1.3, "MPC885-Specific SPRs." Table 4-9
lists user-level special-purpose registers (SPRs).
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Section 4.1.1, "PowerPC Registers—User
Section 4.1.2, "PowerPC
Section 3.2.1, "Levels of the
and Table 2-1
Table 4-1
4-1