Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 592

SDMA Channels and IDMA Emulation
19.2.4 SDMA Address Register (SDAR)
The 32-bit, read-only SDMA address register (SDAR) holds the current system address being accessed
and is used to diagnose an SDMA bus error. SDAR is undefined at reset. Its internal address (IMMR offset)
is 0x904. This register is not affected by HRESET or SRESET.
19.3 IDMA Emulation
The CPM can be configured to emulate two general-purpose independent DMA (IDMA) channels using
one physical SDMA channel. In IDMA emulation mode, the user specifies a memory/memory or
peripheral/memory transfer as if using dedicated DMA hardware.
IDMA uses two addressing modes—dual-address and single-address. In IDMA dual-address transfers,
data is read into internal storage, packed onto the bus, and then written to the destination. Dual-address
transfers can take several bus cycles depending on the peripheral's port size. In contrast, single-address
(fly-by) IDMA bypasses internal storage, transferring data directly between memory and a peripheral in a
single bus cycle. See Section 19.3.8, "IDMA Transfers—Dual-Address and Single-Address."
The IDMA controller supports two buffer handling modes—auto-buffering, and buffer-chaining. In
buffer-chaining, an IDMA moves a connected series of BDs called a chain without interruption.
Auto-buffering allows a buffer chain to be repeatedly transferred in a loop without user intervention. See
Section 19.3.4.2, "Auto-Buffering and Buffer-Chaining."
Note that DREQ0 is the DMA request for IDMA1, and DREQ1 is the DMA request for IDMA2.
19.3.1 IDMA Features
The following is a list of IDMA's main features:
• Two independent, fully programmable DMA channels
• Dual-address or single-address transfers with 32-bit address and data capability
• 32-bit byte transfer counters allow for 4-Gbyte buffers
• Byte, half-word, word, or 4-word burst quantities for transfers
• 32-bit byte-addressable buffer pointers auto-increment for memory accesses and remain constant
for peripheral accesses
• Byte-packing and unpacking algorithms use the absolute minimum number of bus cycles required
during dual-address transfers
• Support for all bus-termination modes, such as TA, TEA, and BI
• DMA handshaking for cycle-steal and burst transfers
• Two buffer handling modes—auto-buffering and buffer-chaining
• The MPC885's chip-select and wait-state generation logic can be used with IDMA.
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MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor