Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 384

External Bus Interface
13.4.2.2 Single-Beat Write Flow
The basic write cycle begins with a bus arbitration, followed by the address transfer, then the data transfer.
The following flow and timing diagrams show the handshakes as applicable to the fixed transaction
protocol. Figure 13-7 maps the flow of a single-beat write cycle.
MASTER SLAVE
Bus Request (BR)
Receives Bus Grant (BG) from arbiter
Asserts Bus Busy (BB) if no other master is driving
Asserts Transfer Start (TS)
Drives address and attributes
Drives data
Asserts Transfer Acknowledge (TA)
Interrupts data driving
Figure 13-7. Basic Flow of a Single-Beat Write Cycle
MPC885 PowerQUICC Family Reference Manual, Rev. 2
13-10 Freescale Semiconductor