Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 282

Instruction Execution Timing
Instructions
Integer trap: twi, tw
Move to: mtspr, mtcrf, mtmsr, mcrxr except mtspr to LR
and CTR and to SPRs external to the core.
Move to LR, CTR: mtspr
Move to SPRs external to core: mtspr, mttb, mttbu. See
Section 9.2.3, "Accessing Off-Core SPRs."
Move from SPRs external to core: mfspr, mftb, mftbu
Move from SPRs internal to core: mfspr
Move from: mfcr, mfmsr
Integer arithmetic: addi, add, addis, subf, addic, subfic,
addic., addc, adde, subfc, subfe, addme, addze,
subfme, subfze, neg
Integer divide: divw, divwu
Integer multiply: mul, mullw, mulhw, mulhwu
Integer compare: cmpi, cmp, cmpli, cmpl
Integer logical: andi., andis., ori, oris, xori, xoris, and,
or, xor, nand, nor, eqv, andc, orc, extsb, extsh, cntlzw
Integer rotate and shift: rlwinm, rlwnm, rlwimi, slw,srw,
srawi, sraw
Integer load: lbz, lbzu, lbzx, lbzux, lhz, lhzu, lhzx, lhzux,
lha, lhau, lhax, lhaux, lwz, lwzu, lwzx, lwzux, lhbrx,
lwbrx.
Integer store: stb, stbu, stbx, stbux, sth, sthu, sthx,
sthux, stw, stwu, stwbrx, stwx, stwux, sthbrx
Integer load/store multiple: lmw, smw
Synchronize: sync
Memory synchronization: lwarx, stwcx.
Move CR from XER: mcrxr
Move to/from SPR (Debug, DAR, DSISR): mtspr, mfspr
String instructions: lswi, lswx, stswi, stswx. See
Section 9.2.2, "String Instruction Latency."
Memory control instructions: isync
9-6
Table 9-1. Instruction Execution Timing (continued)
2
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Latency Blockage
Taken Serialize + 3
serialize + 3
Not taken 1 1
Serialize + 1
1 1
1
Serialize + 1 Serialize + 1
Load latency 1
1
Serialize + 1
1
Min 2 Min 2
5 6
Max 11 Max 11
7
2 1 – 2
1
1
1
8
2 1
1
1 1
Serialize + 1 + no. of registers LSU
Serialize + 1
Serialize + 2
Serialize + 1
Serialize + 1
Serialize + 1 + no. of words
accessed
Serialize
Unit Serializing
IU After
No
All Yes
BPU No
LSU Yes
LSU No
3
— See list
4
— See list
IU No
IU No
IU No
IU No
IU No
IU No
LSU No
LSU No
Yes
LSU Yes
LSU Yes
LSU Yes
LSU Yes
LSU Yes
BPU Yes
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