Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 80

Table
Number
51-1 Interrupt Mask, Status, and Clear Register 1 Signals............................................................ 51-5
51-2 Interrupt Mask, Status, and Clear Register 2 Signals............................................................ 51-5
51-3 Master Control Register Signals ........................................................................................... 51-7
51-4 Master Error Address Register Bit Definitions..................................................................... 51-8
52-1 CPTR SEC Lite–Related Field Descriptions ........................................................................ 52-1
53-1 Fetch Show Cycles Control................................................................................................... 53-3
53-2 Status Pin Groupings............................................................................................................. 53-3
53-3 VF Pins Encoding: Instruction Queue Flushes ..................................................................... 53-3
53-4 VF Pins Encoding: Instruction Fetch Types.......................................................................... 53-4
53-5 Detecting the Trace Buffer Start Point .................................................................................. 53-7
53-6 Instruction Watchpoints Programming Options.................................................................. 53-11
53-7 Load/Store Data Events....................................................................................................... 53-13
53-8 Load/Store Watchpoints Programming Options ................................................................. 53-13
53-9 Checkstop State and Debug Mode ...................................................................................... 53-22
53-10 Trap Enable Data Shifted into Development Port Shift Register ....................................... 53-29
53-11 Debug Port Command Shifted Into Development Port Shift Register ............................... 53-29
53-12 Status/Data Shifted Out of Development Port Shift Register ............................................. 53-30
53-13 Debug Instructions/Data Shifted Into Development Port Shift Register ............................ 53-31
53-14 MPC885-Specific Development Support and Debug SPRs ............................................... 53-34
53-15 Development Support/Debug Registers Protection ............................................................ 53-35
53-16 CMPA–CMPD Field Descriptions ...................................................................................... 53-35
53-17 CMPE–CMPF Field Descriptions....................................................................................... 53-36
53-18 CMPG–CMPH Field Descriptions...................................................................................... 53-36
53-19 BAR Field Descriptions ...................................................................................................... 53-37
53-20 ICTRL Field Descriptions................................................................................................... 53-37
53-21 LCTRL1 Field Descriptions................................................................................................ 53-39
53-22 LCTRL2 Field Descriptions................................................................................................ 53-40
53-23 COUNTA/COUNTB Field Descriptions ............................................................................ 53-42
53-24 ICR Field Descriptions........................................................................................................ 53-43
53-25 DER Field Descriptions ...................................................................................................... 53-45
54-1 Instruction Register Decoding .............................................................................................. 54-6
A-1 Byte-Ordering Parameters...................................................................................................... A-1
A-2 TLE 2-bit Munging ................................................................................................................ A-3
A-3 Little-Endian Program/Data Path Between the Register and 32-Bit Memory....................... A-4
A-4 Little-Endian Program/Data Path Between the Register and 16-Bit Memory....................... A-4
A-5 Little-Endian Program/Data Path between the Register and 8-Bit Memory ......................... A-5
A-6 PPC-LE 3-bit Munging .......................................................................................................... A-6
C-1 User-Level Registers...............................................................................................................C-1
C-2 User-Level SPRs .....................................................................................................................C-1
C-3 Supervisor-Level Registers .....................................................................................................C-2
C-4 Supervisor-Level SPRs ...........................................................................................................C-2
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Tables
Title
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Page
Number
Freescale Semiconductor