Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 700

Powerquicc family

Table of Contents

SCC HDLC Mode

Table 23-1. HDLC-Specific SCC Parameter RAM Memory Map (continued)

From SCC base. SCC base = IMMR + 0x3D00 (SCC2) or 0x3E00 (SCC3) or 0x3F00 (SCC4)

shows 16- and 8-bit address recognition.

16-Bit Address Recognition

Recognizes one 16-bit address (HADDR1) and

the 16-bit broadcast address (HADDR2)

Max frame length register. The HDLC compares the incoming HDLC frame's length

with the user-defined limit in MFLR. If the limit is exceeded, the rest of the frame is

discarded and RxBD[LG] is set in the last BD of that frame. At the end of the frame

the SCC reports frame status and frame length in the last RxBD. The MFLR is

defined as all in-frame bytes between the opening and closing flags.

Maximum length counter. A temporary down-counter used to track frame length.

Received frames threshold. Used to reduce potential interrupt overhead when

each in a series of short HDLC frames causes an SCCE[RXF] event. Setting

RFTHR determines the frequency of RXF interrupts, which occur only when the

RFTHR limit is reached. Provide enough empty RxBDs for the number of frames

specified in RFTHR.

Received frames count. RFCNT is a down-counter used to implement RFTHR.

Mask register (HMASK) and four address registers (HADDR n ) for address

recognition. The SCC reads the frame address from the HDLC receiver, compares

it with the HADDRs, and masks the result with HMASK. Setting an HMASK bit

enables the corresponding comparison bit, clearing a bit masks it. When a match

occurs, the frame address and data are written to the buffers. When no match

occurs and a frame is error-free, the nonmatching address received counter

(NMARC) is incremented.

The eight low-order bits of HADDR n should contain the first address byte after the

opening flag. For example, to recognize a frame that begins 0x7E (flag), 0x68,

0xAA, using 16-bit address recognition, HADDR n should contain 0xAA68 and

HMASK should contain 0xFFFF. For 8-bit addresses, clear the eight high-order

HMASK bits. See Figure 23-2..

Temporary storage.

Temporary storage.

Figure 23-2. HDLC Address Recognition

MPC885 PowerQUICC Family Reference Manual, Rev. 2

8-Bit Address Recognition

Recognizes a single 8-bit address (HADDR1)

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