Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 948

CPM Interrupt Controller
• If SPS = 0, the USB and 3 SCC priorities are spread over the table so other sources can have lower
interrupt latencies than the USB and SCCs.
35.2.2 Highest Priority Interrupt
The highest priority interrupt source can be selected dynamically by entering the interrupt number in
CICR[HPn], described in
CICR[IRL] but is serviced before any other CPM interrupt (that is, if this type of interrupt is pending, its
vector number returns first when the CIVR is read.
35.2.3 Nested Interrupts
The CPIC supports a fully nested interrupt environment that allows a high priority interrupt from another
CPM source to suspend a lower priority service routine. An interrupt request with highest priority is
presented to the core for servicing, which the core acknowledges by setting CIVR[IACK]. After IACK is
set, the corresponding vector is indicated in the CIVR and the request is cleared. The next request can be
presented to the core. When the interrupt is taken, the external interrupt enable bit of the core's machine
state register, MSR[EE] is cleared to disable further interrupt requests until software can handle them.
The CPM interrupt in-service register (CISR) can be used to allow a higher priority interrupt within the
same interrupt level to be presented to the core before a lower priority interrupt service completes. Each
CISR bit corresponds to a CPM interrupt source. When the core acknowledges the interrupt by setting
IACK, the CPIC sets the CISR bit for that interrupt source. This prevents subsequent CPM interrupt
requests at this priority level or lower, until the current interrupt is serviced and the CISR bit is cleared.
Lower-priority interrupts can still be set in the CPIC during this time, but they will pend until the CISR bit
for the higher-priority interrupt is cleared. Therefore, in the interrupt service routine for the CPM
interrupts, the core external interrupt enable MSR[EE] can be set to allow higher-priority interrupts within
the CPM or from other sources to generate an interrupt request.
35.3 Masking Interrupt Sources in the CPM
An interrupt is masked by clearing and enabled by setting the corresponding CIMR bit; see
"CPM Interrupt Mask Register."
is set but the CPIC does not signal the interrupt to the core. Masking all sources allows the implementation
of a polling interrupt servicing scheme.
CPM sub-blocks with multiple interrupting events can be masked individually by programming a mask
register within that block (such as the SMC UART register (SMCM), described in
UART Event Register (SMCE)/Mask Register
have multiple interrupting events.
35-4
Table 35-3. This interrupt is still within the same interrupt level specified in
When a masked source requests an interrupt, the corresponding CIPR bit
(SMCM)").
Figure 35-2 shows masking using the SMC sub-block.
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Section 29.3.12, "SMC
Table 35-2 shows the interrupt sources that
Section 35.5.3,
Freescale Semiconductor