Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 147

3.4.2 Basic Instruction Pipeline
Figure 3-3 shows instruction pipeline timing, showing how by distributing the processes required to fetch,
execute, and retire an instruction into stages, multiple instructions can be processed during a single clock
cycle.
Gclk1
Fetch
Decode
Read + Execute
Writeback
L Address Drive
L Data
Load Write Back
3.4.3 Instruction Unit
The instruction unit implements the basic instruction pipeline, fetches instructions from the memory
system, dispatches them to available execution units, and maintains a state history to ensure a precise
exception model and that operations finish in order. The instruction unit implements all branch processor
instructions, including flow control and CR instructions. Table 9-1 on page 9-5 in Chapter 9 describes
instruction latencies.
3.4.3.1 Branch Operations
Because branch instructions can change program flow and because most branches cannot be resolved at
the same time they are fetched, program branching can keep a processor from operating at maximum
instruction throughput.
If a branch is mispredicted, additional time is required to flush the incorrect branch instructions and begin
fetching from the correct target stream, which can create bubbles in the pipeline. To reduce the latency
caused by misprediction, branch instructions allow the programmer to indicate whether a branch is likely
to be taken. This is called static branch prediction.
Freescale Semiconductor
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Figure 3-3. Basic Instruction Pipeline Timing
MPC885 PowerQUICC Family Reference Manual, Rev. 2
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The MPC8xx Core
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