Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 565

17.2.4.4 Timer Event Registers (TER1–TER4)
Each timer event register (TER1–TER4), shown in
When an output reference event is recognized, the timer sets TERx[REF] regardless of the corresponding
TMRx[ORI]. The capture event is set only if it is enabled in TMRx[CE].
Writing ones clears event bits; writing zeros has no effect. Both event bits must be cleared before the timer
negates the interrupt to the CPIC. These registers are affected by HRESET and SRESET.
0
Field
Reset
R/W
Addr
Table 17-3 describes the TER fields.
Bits Name
0–13 — Reserved, should be cleared.
14 REF Output reference event. When set, indicates the counter reached the value in the TRR. TMR[ORI] is
used to enable the interrupt request caused by this event.
15 CAP Capture event. Indicates that the counter value has been latched into the TCR. TMR[CE] enables
generation of this event.
17.2.5 Timer Initialization Examples
The following two initialization sequences program timer 2 to generate an interrupt every 10 µs. The first
sequence uses timer 2 alone, while the second example uses timers 1 and 2 in cascaded mode. Assuming
a 25-MHz general system clock, an interrupt should be generated every 250 system clocks.
1. Set TGCR = 0x0000 to reset timer 2.
2. Set TMR2 = 0x001A to set the prescaler to divide by 1 and the clock source to the general system
clock. This value also enables an interrupt when the timer reaches the reference count and
immediately clears (restarts) the TCN for the next interrupt.
3. Set TCN2 = 0x0000 to clear the timer 2 counter (default).
4. Set TRR2 = 0x00FA to initialize the timer 2 reference value to 250.
5. Write TER2 = 0xFFFF to clear TER2 of any previous events.
6. Set CIMR = 0x0004_0000 to enable timer 2 interrupts in the CPIC and initialize the CICR.
7. Set TGCR = 0x0010 to enable timer 2 to begin counting.
Freescale Semiconductor
Figure
—
0x9B0 (TER1), 0x9B2 (TER2), 0x9B4 (TER3), 0x9B6 (TER4)
Figure 17-10. Timer Event Registers (TER1–TER4)
Table 17-3. TER Field Descriptions
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Communications Processor Module and CPM Timers
17-10, reports events recognized by the timers.
0
R/W
Description
13 14 15
REF CAP
17-11