Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 823

29.4.11 SMC Transparent Event Register (SMCE)/Mask Register (SMCM)
The SMC event register (SMCE) generates interrupts and reports events recognized by the SMC channel.
When an event is recognized, the SMC sets the corresponding SMCE bit. Interrupts are masked in the
SMCM, which has the same format as the SMCE. SMCE bits are cleared by writing ones; writing zeros
has no effect. Unmasked bits must be cleared before the CP clears the internal interrupt request.
Figure 29-15 shows the SMCE/SMCM register format.
0
Field
Reset
R/W
Address
Figure 29-15. SMC Transparent Event Register (SMCE)/Mask Register (SMCM)
Table 29-16 describes SMCE/SMCM fields.
Bits Name
0–2 — Reserved, should be cleared.
3 TXE Tx error. Set when an underrun error occurs on the transmitter channel.
4 — Reserved, should be cleared.
5 BSY Busy condition. Set when a character is received and discarded due to a lack of buffers. Reception
begins after a new buffer is provided, without waiting for resynchronization. To resynchronize after
error recovery, issue an
6 TX Tx buffer. Set after a buffer is sent. If the L bit of the TxBD is set, TX is set when the last character
starts being sent. A one character-time delay is required to ensure that data is completely sent over
the transmit pin. If the L bit of the TxBD is cleared, TX is set when the last character is written to the
transmit FIFO. A two character-time delay is required to ensure that data is completely sent.
7 RX Rx buffer. Set when a buffer is received (after the last character is written) on the SMC channel and
its associated RxBD is closed.
29.4.12 SMC Transparent NMSI Programming Example
The following example initializes the SMC1 transparent channel over its own set of pins. The CLK3 pin
supplies the transmit and receive clocks; the SMSYNx pin is used for synchronization. The SMC UART
example shows baud-rate generator configuration.
1. Configure the port B pins to enable SMTXD1, SMRXD1, and SMSYN1. Set PBPAR[23– 25] and
clear PBDIR[23– 25] and PBODR[23– 25].
2. Configure the port A pins to enable CLK3. Set PAPAR[5] and clear PADIR[5]. The other pin
functions are the timers or the TSA. These alternate functions cannot be used on this pin.
3. Connect CLK3 to SMC1 using the SI. Clear SIMODE[SMC1] and set SIMODE[SMC1CS] to
0b110.
Freescale Semiconductor
2 3
— TXE
0xA86 (SMCE1), 0xA96 (SMCE2)/ 0xA8A (SMCM1), 0xA9A (SMCM2)
Table 29-16. SMCE/SMCM Field Descriptions
ENTER HUNT MODE
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Serial Management Controllers (SMCs)
4 5
— BSY
0
R/W
Description
command.
6 7
TX RX
29-29