Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 444

Memory Controller
15.2 Basic Architecture
The memory controller consists of three basic machines:
• General-purpose chip-select machine (GPCM)
• User-programmable machine A (UPMA)
• User-programmable machine B (UPMB)
Each bank can be assigned to any one of these machines via the BRx[MS] bits as shown in
Address decode is performed by the comparison of (A[0:16] bit-wise and ORx[AM]) with BRx[BA]. If an
address match occurs in multiple banks, the lowest numbered bank has priority. When a memory address
matches BRx[BA], the corresponding machine takes ownership of the external signals that control access
until the cycle ends.
Bank 0
Bank 1
Bank 2
Bank 3
Bank 4
Bank 5
Bank 6
Bank 7
The GPCM provides a glueless interface to EPROM, SRAM, flash EPROM, and other peripherals. GPCM
signals are available on CS[0:7]. CS0 lets the CPU access the boot EPROM from reset. Each chip-select
allows up to 30 wait states.
Some features are common to all eight memory banks:
• The block size of each memory bank can vary between 32 Kbytes and 256 Mbytes for a full 4
Gbytes of the address space.
• Each memory bank can be selected for read-only or read/write operation.
• For system protection, access to a memory bank can be restricted to accesses with certain address
type codes (AT[0:2]). For additional flexibility, address-type comparisons provide a mask option.
The memory controller functionality minimizes the need for glue logic in MPC885-based systems. In
Figure 15-3, CS0 is used with the 16-bit boot EPROM with BR0[MS] defaulting to select the GPCM. CS1
15-4
BR0[MS]
BR1[MS]
BR2[MS]
BR3[MS]
BR4[MS]
BR5[MS]
BR6[MS]
BR7[MS]
Figure 15-2. Memory Controller Machine Selection
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Figure 15-2.
UPMA
UPMB
GPCM
Freescale Semiconductor