Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 214

Instruction and Data Caches
• Both caches can be disabled, invalidated, or locked by issuing commands to their respective cache
control registers, special-purpose registers (SPRs) specific to the MPC885. See
"Cache Control Registers,"
• Individual cache blocks can be locked so that frequently accessed instructions or data are
guaranteed to be resident in the respective cache.
On a cache miss, the MPC885 cache blocks are filled in 16-byte bursts. The burst fill is performed as a
critical-word-first operation; the critical word is simultaneously written to the cache and forwarded to the
requesting unit, thus minimizing stalls due to cache fill latency. Both caches provide storage for cache tags
and perform cache block replacement (LRU) function.
Both caches are tightly coupled to the MPC885 system interface unit (SIU) to allow efficient access to the
system memory controller and other bus masters. The SIU receives requests for bus operations from the
instruction and data caches and executes the operations according to the external bus protocol.
The data cache provides buffers for load and store bus operations. The data cache supplies data to the GPRs
by means of a 32-bit interface to the load/store unit. The LSU is directly coupled to the data cache to allow
efficient movement of data to and from the general-purpose registers. The load/store unit provides all logic
required to calculate effective addresses, handles data alignment to and from the data cache, and provides
sequencing for load and store string and multiple operations. Write operations to the data cache can be
performed on a byte, half-word, or word basis.
The instruction cache provides a 32-bit interface to the instruction sequencer. The instruction sequencer
uses the instruction cache as much as possible in order to sustain the high throughput provided by the
four-entry instruction queue.
7.1 Instruction Cache Organization
The MPC885 instruction cache is organized as 256 sets of two blocks, as shown in
consists of 16 bytes, a single state bit, a lock bit, and an address tag.
7-2
for more information.
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Section 7.3,
Figure 7-1. Each block
Freescale Semiconductor