Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 311

Table 10-15 describes the DEC register.
Bits Name
0–31 DEC Decrementer. These bits are used by a down counter to cause decrementer interrupts. Reading
DEC always returns the current count value from the down counter.
10.9 Timebase
The timebase is a 64-bit free-running binary counter as defined in the PowerPC architecture. For the
MPC885, the timebase is clocked by TMBCLK. The timebase period is as follows:
The timebase is unaffected by HRESET and SRESET and should be initialized by software. PORESET,
however, disables and resets the timebase. The entire timebase cannot be accessed with a single
instruction; mttb and mftb access the lower half of the timebase and mttbu and mftbu access the upper
half. A maskable interrupt is generated when the timebase count reaches a value programmed in one of the
reference registers, TBREFA and TBREFB; two status bits indicate which one caused the interrupt.
10.9.1 Timebase Register (TBU and TBL)
The timebase register (TB) holds a 64-bit integer that is incremented periodically. It is implemented in two
parts, time base upper and time base lower (TBU and TBL). There is no automatic initialization of TB,
therefore, system software must perform this initialization. The contents of TB can be written by mtspr
and read by mftb or mftbu instruction.
registers. They must be unlocked in TBK before they can be written.
0
Field
Reset
R/W
SPR
Table 10-16 describes TBU fields.
Bits Name
0–31 TBU Timebase upper. The value in this field is used as an upper part of the timebase counter.
Freescale Semiconductor
Table 10-15. DEC Field Descriptions
T = ---------------------- -
TB
F
Figure 10-19
269 (Read)/285 (Write)
Figure 10-19. Timebase Upper Register (TBU)
Table 10-16. TBU Field Descriptions
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Description
2 64
tmbclk
shows TBU. Note that the TBU and TBL are keyed
TBU
—
R/W
Description
System Interface Unit
31
10-23