Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 683

22.14 Fractional Stop Bits (Transmitter)
The asynchronous UART transmitter can be programmed to send fractional stop bits. The FSB field in the
data synchronization register (DSR) determines the fractional length of the last stop bit to be sent. FSB can
be modified at any time. If two stop bits are sent, only the second is affected. Idle characters are always
sent as full-length characters.
0 1
Field —
Reset 0
R/W
Addr
Table 22-6 describes DSR fields.
Bit Name
0 — 0b0
1–4 FSB Fractional stop bits. For 16× oversampling:
For 32× oversampling:
For 8× oversampling:
The UART receiver can always receive fractional stop bits. The next character's start bit can begin
any time after the three middle samples have been taken.
5–6 — 0b11
7–8 — 0b00
9–14 — 0b111111
15 — 0b0
Freescale Semiconductor
4 5 6
FSB — —
1 1 1
0xA2E (DSR2), 0xA4E (DSR3), 0xA6E (DSR4)
Figure 22-5. Data Synchronization Register (DSR)
Table 22-6. DSR Fields Descriptions
1111 Last transmitted stop bit 16/16. Default value after reset.
1110 Last transmitted stop bit 15/16
...
1000 Last transmitted stop bit 9/16
0xxx Invalid. Do not use.
1111 Last transmitted stop bit 32/32. Default value after reset.
1110 Last transmitted stop bit 31/32
...
0000 Last transmitted stop bit 17/32
1111 Last transmitted stop bit 8/8. Default value after reset.
1110 Last transmitted stop bit 7/8
1101 Last transmitted stop bit 6/8
1100 Last transmitted stop bit 5/8
10xx Invalid. Do not use.
0xxx Invalid. Do not use.
MPC885 PowerQUICC Family Reference Manual, Rev. 2
7 8 9 10 11
— — — — —
0 0 1 1 1
R/W
Description
SCC UART Mode
12 13 14 15
— — — —
1 1 1 0
22-11