Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 753

0
Field —
Reset
R/W
Addr 0xA30 (SCCE2)/0xA34 (SCCM2); 0xA50 (SCCE3)/0xA54 (SCCM3); 0xA70 (SCCE4)/0xA74 (SCCM4)
Figure 26-8. BISYNC Event Register (SCCE)/BISYNC Mask Register (SCCM)
Table 26-13 describes SCCE and SCCM fields.
Bits Name
0–2 — Reserved, should be cleared.
3 GLR Glitch on Rx. Set when the SCC finds an Rx clock glitch.
4 GLT Glitch on Tx. Set when the SCC finds a Tx clock glitch.
5 DCC DPLL CS changed. Set when carrier sense status generated by the DPLL changes. Real-time
status can be found in SCCS. This is not the CD status discussed elsewhere. Valid only when DPLL
is used.
6–7 — Reserved, should be cleared.
8 GRA Graceful stop complete. Set as soon the transmitter finishes any message in progress when a
GRACEFUL STOP TRANSMIT
9–10 — Reserved, should be cleared.
11 TXE Tx Error. Set when an error occurs on the transmitter channel.
12 RCH Receive character. Set when a character is received and written to the buffer.
13 BSY Busy. Set when a character is received and discarded due to a lack of buffers. The receiver resumes
reception after an
14 TXB Tx buffer. Set when a buffer is sent. TXB is set as the last bit of data or the BCS begins transmission.
15 RXB Rx buffer. Set when the CPM closes the receive buffer on the BISYNC channel.
26.15 SCC Status Registers (SCCS)
The SCC status (SCCS) register allows real-time monitoring of RXD. The real-time status of CTS and CD
are part of the port C parallel I/O.
0
Field
Reset
R/W
Addr
Freescale Semiconductor
2 3 4 5 6
GLR GLT DCC
0000_0000_0000_0000
Table 26-13. SCCE/SCCM Field Descriptions
is issued (immediately if no message is in progress).
ENTER HUNT MODE
—
0xA37 (SCCS2), 0xA57 (SCCS3), 0xA77 (SCCS4)
Figure 26-9. SCC Status Registers (SCCS)
MPC885 PowerQUICC Family Reference Manual, Rev. 2
7 8 9 10
— GRA —
R/W
Description
command.
5
0000_0000
R
SCC BISYNC Mode
11 12 13 14 15
TXE RCH BSY TXB RXB
6 7
CS —
26-15