Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 889

2
32.4.2 I C Address Register (I2ADD)
2
The I C address register, shown in
0
Field
Reset
R/W
Addr
This register is not affected by HRESET or SRESET.
Bits Name
0–6 SAD Slave address 0–6. Holds the slave address for the I
7 — Reserved and should be cleared.
2
32.4.3 I C Baud Rate Generator Register (I2BRG)
2
The I C baud rate generator register, shown in
0
Field
Reset
R/W
Addr
This register is affected by HRESET but is not affected by SRESET.
Bits Name
0–7 DIV Division ratio 0–7. Specifies the divide ratio of the BRG divider in the I
of the prescaler is divided by 2 * ([DIV0–DIV7] + 3) and the clock has a 50% duty cycle. DIV must
be programmed to a minimum value of 3 if the digital filter is disabled and 6 if it is enabled.
2
32.4.4 I C Event/Mask Registers (I2CER/I2CMR)
2
The I C event register (I2CER) is used to generate interrupts and report events. When an event is
2
recognized, the I C controller sets the corresponding I2CER bit. I2CER bits are cleared by writing
ones—writing zeros has no effect. Setting a bit in the I
Freescale Semiconductor
Figure 32-7, holds the address for this I
SAD
2
Figure 32-7. I C Address Register (I2ADD)
Table 32-2. I2ADD Field Descriptions
Figure
2
Figure 32-8. I C Baud Rate Generator Register (I2BRG)
Table 32-3. I2BRG Field Descriptions
MPC885 PowerQUICC Family Reference Manual, Rev. 2
2
C port.
Undefined
R/W
0x864
Table 32-2 describes I2CADD fields.
Description
2
C port.
32-8, sets the divide ratio of the I
DIV
1111_1111
R/W
0x868
Table 32-3
Description
2
2
C mask register (I2CMR) enables and clearing a
2
I C Controller
6 7
—
2
C BRG.
7
describes I2BRG fields.
C clock generator. The output
32-7