Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 615

Note that when using a single TDM channel, the entire SI RAM is available to TDMa, whereas only the
last half of each Rx or Tx RAM is accessible to TDMb; that is, the TDMb SI RAM area always begins at
byte 128 for receive and byte 384 for transmit; see Figure 20-6. Furthermore, if the user wants to use only
TDMb, the SI RAM must still be programmed for both TDM channels (with TDMa left uninitialized and
disabled). Also note that the SI RAM is uninitialized after power-on—the core should program them
before enabling the TDM channels.
20.2.3.1 Disabling and Reenabling the TSA
The following steps must be taken any time the TSA is disabled. These steps also apply to changing the
SI routing when the TSA is configured for static frames.
1. SCC and SMC connections to the TSA must be disabled.
2. The SI configuration can be modified.
3. SCC and SMC connections to the TSA must be reenabled.
20.2.3.2 One TDM Channel with Static Frames
In an SI configuration using one multiplexed channel with static frames, shown in
64 entries in the SI RAM for Rx data/strobe routing and 64 entries for Tx data/strobe routing. Note that
only TDMa can use the entire SI RAM.
Figure 20-5. SI RAM Partitioning Using TDMa with Static Frames
20.2.3.3 Two TDM Channels with Static Frames
In a configuration with two multiplexed channels with static frames, shown in
entries for Tx data/strobe routing and 32 entries for Rx data/strobe routing for each TDM channel.
Freescale Semiconductor
RDM = 00
One Channel (TDMa) with Independent Rx and Tx Route
SI RAM Address: 0
(32-Bit Entries)
64 Entries
Route
255
256
64 Entries
Route
511
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Framing Signals
L1RCLKa
L1RSYNCa
Rxa
L1TCLKa
L1TSYNCa
Txa
Serial Interface
Figure 20-5, there are
Figure 20-6, there are 32
20-9