Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 184

MPC885 Instruction Set
Load string and store string instructions may involve operands that are not word-aligned. As described in
"Alignment Exception (0x00600)" in Chapter 6, "Exceptions," in the Programming Environments
Manual, a misaligned string operation suffers a performance penalty compared to a word-aligned
operation of the same type.
When a string operation crosses a page boundary, the instruction may be interrupted by a DSI exception
associated with the address translation of the second page. In this case, the MPC885 performs some or all
memory references from the first page and none from the second before taking the exception. On return
from the DSI exception, the load or store string instruction will re-execute from the beginning. For more
information, refer to "DSI Exception (0x00300)" in Chapter 6, "Exceptions," in the Programming
Environments Manual.
5.2.4.3 Branch and Flow Control Instructions
Branch instructions are executed by the branch processing unit (BPU). The BPU receives branch
instructions from the fetch unit and performs condition register (CR) lookahead operations on conditional
branches to resolve them early, achieving the effect of a zero-cycle branch in many cases.
Some branch instructions can redirect instruction execution conditionally based on the value of bits in the
CR. When the branch processor encounters one of these instructions, it scans the execution pipelines to
determine whether an instruction in progress may affect the particular CR bit. If no interlock is found, the
branch can be resolved immediately by checking the bit in the CR and taking the action defined for the
branch instruction.
If an interlock is detected, the branch is considered unresolved and the direction of the branch is predicted
using static branch prediction as described in "Conditional Branch Control" in Chapter 4, "Addressing
Modes and Instruction Set Summary," in the Programming Environments Manual. The interlock is
monitored while instructions are fetched for the predicted branch. When the interlock is cleared, the branch
processor determines whether the prediction was correct based on the value of the CR bit. If the prediction
is correct, the branch is considered completed and instruction fetching continues. If the prediction is
incorrect, the fetched instructions are purged, and instruction fetching continues along the alternate path.
See Chapter 9, "Instruction Execution Timing,"
5.2.4.3.1 Branch Instruction Address Calculation
Branch instructions can alter the sequence of instruction execution. Instruction addresses are always
assumed to be word aligned; the processor ignores the two low-order bits of the generated branch target
address.
Branch instructions compute the effective address (EA) of the next instruction address using the following
addressing modes:
• Branch relative
• Branch conditional to relative address
• Branch to absolute address
• Branch conditional to absolute address
5-14
for information about how branches are executed.
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor