Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 887

3. After the first byte is shifted in, the slave compares the received data to its slave address. If the slave
is an MPC885, the address is programmed in its I
— If a match is found and the slave is ready, then the slave acknowledges the request and begins
sending on the clock pulse after the acknowledge. If the slave is an MPC885, it is ready when
its transmit FIFO has been loaded by the SDMA channel (the transmit buffers and BDs have
been prepared and I2COM[STR] has been set).
— If a match is found but the slave is not ready, the read request is not acknowledged and the
transaction is aborted. If the slave is an MPC885, a maskable transmission error interrupt is
triggered to allow software to prepare data for transmission on the next try.
— If a mismatch occurs, the slave ignores the message and searches for a new start condition.
4. The master acknowledges each byte sent as long as an overrun does not occur. If the master
receiver fails to acknowledge a byte, the slave aborts transmission. For a slave MPC885, the abort
generates a maskable interrupt. A maskable interrupt is also issued after a complete buffer is sent
or after an error. If an underrun occurs, the MPC885 slave sends ones until a stop condition is
detected.
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32.3.4 I C Multi-Master Considerations
2
The I C controller supports a multi-master configuration, in which the I
between master and slave modes. The I
in hardware. However, due to the nature of the I
software considerations must be made.
2
An MPC885 I C controller attempting a master read request could simultaneously be targeted for an
external master write (slave read). Both operations trigger the controller's I2CER[RXB] event, but only
one operation wins the bus arbitration. To determine which operation caused the interrupt, software must
verify that its transmit operation actually completed before assuming that the received data is the result of
its read operation.
Problems could also arise if the MPC885's I
write request, but then is the target of a read request from another master. Without software precautions,
2
the I C controller responds to the other master with the transmit buffer originally intended for its own write
request. To avoid this situation, a higher-level handshake protocol must be used. For example, a master,
before reading a slave, writes the slave with a description of the requested data (which register should be
read, for example). This operation is typical with many I
2
32.4 I C Registers
The following sections describe the I
Freescale Semiconductor
2
C controller supports this by implementing I
2
C bus and the implementation of the I
2
C controller master sets up a transmit buffer and BD for a
2
C registers.
MPC885 PowerQUICC Family Reference Manual, Rev. 2
2
C address register (I2ADD).
2
C controller must alternate
2
C devices.
2
I C Controller
2
C master arbitration
2
C controller, certain
32-5