Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 932

Parallel I/O Ports
After connecting CTS or CD to the SCC, choose normal operation mode in GSMR[DIAG] to enable or
disable SCC transmission and reception with these signals.
PC14 and PC15 can be programmed to assert special requests directly to the CPM by setting RCCR[EIE];
however, do not do so unless instructed by a Motorola-supplied RAM microcode package.
For IDMA, PC14 and PC15 can be programmed to function as external DMA request (DREQx) signals.
Do not configure PC14and PC15 as DREQ1 and DREQ0 unless IDMA is initialized; otherwise, erratic
operation can occur.
34.4.1 Port C Registers
Port C is supported by five registers. The port C interrupt control register (PCINT) defines how changes
on the signal cause interrupts when they are generated with that signal. The port C special options register
(PCSO) determines whether certain port C signals can connect to on-chip peripherals and generate an
interrupt at the same time. The remaining port C registers (PCDAT, PCDIR, and PCPAR) have the same
functions as their counterparts on ports A and B. Port C has no open-drain capability.
34.4.1.1 Port C Data Register (PCDAT)
When read, the port C data (PCDAT) register always reflects the current status of each line.
0
Field —
Reset
R/W
Addr
This register is not affected by HRESET or SRESET.
Bits Name
0–3 — Reserved
4–15 D n Contains the data on the corresponding signal
34.4.1.2 Port C Data Direction Register (PCDIR)
Port C data direction register (PCDIR) bits configure port C signals as general-purpose inputs or outputs.
If a signal is not programmed for general-purpose I/O, PCDIR, along with PCSO, selects the peripheral
function to be performed.
34-14
3 4 5 6
D4 D5 D6
0000_0000_0000_0000
Figure 34-11. Port C Data Register (PCDAT)
Table 34-13. PCDAT Bit Descriptions
MPC885 PowerQUICC Family Reference Manual, Rev. 2
7 8 9 10 11
D7 D8 D9 D10 D11
R/W
0x966
Table 34-13 describes PCDAT bits.
Description
12 13 14 15
D12 D13 D14 D15
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