Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 321

Powerquicc family
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0
1
Field EHRS ESRS
Reset
R/W
16
Field
Reset
R/W
The RSR bits are described in
are cleared by writing ones; writing zeros has no effect.
Bits
Name
0
EHRS
External hard reset status. Set by a power-on reset. When an external hard reset event is
detected, EHRS is set and remains set until software clears it.
0 No external hard reset event occurred.
1 An external hard reset event occurred.
1
ESRS
External soft reset status. Set by a power-on reset. When an external soft reset event is detected,
ESRS is set and remains set until software clears it.
0 No external soft reset event occurred.
1 An external soft reset event occurred.
2
Reserved
3
SWRS
Software watchdog reset status. Cleared by a power-on reset. When a software watchdog expire
event occurs, SWRS is set and remains set until software clears it.
0 No software watchdog reset event occurred.
1 A software watchdog reset event occurred.
4
CSRS
Check stop reset status. Cleared by a power-on reset. When the core enters the checkstop state
and the checkstop reset is enabled by PLPRCR[CSR], CSRS is set and remains set until
software clears it.
0 No enabled checkstop reset event occurred.
1 An enabled checkstop reset event occurred.
5
DBHRS
Debug port hard reset status. Cleared by a power-on reset. When the debug port hard reset
request is set, DBHRS is set and remains set until software clears it.
0 No debug port hard reset request occurred.
1 A debug port hard reset request occurred.
6
DBSRS
Debug port soft reset status. Cleared by a power-on reset. When the debug port soft reset
request is set, DBSRS is set and remains set until software clears it.
0 No debug port soft reset request occurred.
1 A debug port soft reset request occurred.
Freescale Semiconductor
2
3
4
5
SWRS CSRS DBHRS DBSRS JTRS
1100_0000_0000_0000
0000_0000_0000_0000
Figure 11-3. Reset Status Register (RSR)
Table
11-2. Note that the bits in this register (except those that are reserved)
Table 11-2. Reset Status Register Bit Settings
MPC885 PowerQUICC Family Reference Manual, Rev. 2
6
7
8
R/W
R/W
Description
Reset
15
31
11-5

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