Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 409

13.4.9 Memory Reservation
The MPC885 memory reservation protocol supports multilevel bus structures. For each local bus,
reservations are handled by the local reservation logic. The protocol tries to optimize reservation
cancellation such that an MPC8xx core processor is notified of memory reservation loss on a remote bus
only when it has issued a STWCX cycle to that address. That is, the reservation loss indication comes as
part of the STWCX cycle, which avoids the need for fast memory reservation loss indication signals
between each remote bus and each MPC8xx master. The memory reservation protocol assumes the
following:
• Each processor has no more than one reservation flag.
• lwarx sets the reservation flag.
• lwarx by the same processor clears the reservation flag related to a previous lwarx instruction and
again sets the reservation flag.
• stwcx. by the same processor clears the reservation flag.
• Store by the same processor does not clear the reservation flag.
• Some other processor (or other mechanism) store to the same address as an existing reservation
clears the reservation flag.
• If memory reservation is lost, it is guaranteed that stwcx. will not modify the memory.
13.4.9.1 Cancel Reservation (CR)
CR is a point-to-point signal. To use it, reservation logic must remember specifically which bus master
requested reservation for which address. If another master writes to the reserved address, the reservation
logic asserts CR only to the master that holds the associated reservation, thus clearing its flag.
The advantage of CR is that it preempts the stwcx. instruction if reservation is lost, thus eliminating
unnecessary traffic on the external bus.
Figure 13-27 shows the reservation protocol for a single-level (local) bus. It assumes that an external logic
on the bus handles the following:
• Snoops accesses to all local bus slaves.
• Holds one reservation for each local master capable of memory reservations.
• Sets the reservation when that master issues a load and reserve request.
• Clears the reservation when another master issues a store to the reservation address.
Freescale Semiconductor
MPC885 PowerQUICC Family Reference Manual, Rev. 2
External Bus Interface
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