Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 476

Memory Controller
The examples in Figure 15-36
UPM RAM words determine the values of the CST[1–4], G1T3, G1T4, G2T3, and G2T4 bits, which
specify the timing of chip-selects, byte-selects, and GPL signals based on the edges of GCLK1_50 or
GCLK2_50. The clock phases shown refer to the timing windows when the signals controlled by these bits
in the RAM word are driven.
Internal
System Clock
CLKOUT
GCLK1_50
GCLK2_50
CS
GPL1
GPL2
Clock Phase
Figure 15-36. UPM Signals Timing Example One (Division Factor = 1, EBDF = 00)
15-36
and Figure 15-37 show how to control the timing of CS, GPL1, and GPL2.
CST4 CST1 CST2
G1T4
G2T4
1 2 3
RAM Word
MPC885 PowerQUICC Family Reference Manual, Rev. 2
CST3 CST4 CST1
G1T3 G1T4 G1T4
G2T3 G2T4 G1T4
4 1 2
RAM Word
CST2 CST3
G1T3
G2T3
3 4
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