Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 240

Instruction and Data Caches
When the MPC885 is in debug mode, all instructions are fetched from the development port, regardless of
the address generated by the MPC885 core. Therefore, the instruction cache is bypassed when the
MPC885 is in debug mode. In addition, the data cache is frozen in debug mode. Loads and stores in debug
mode always target system memory, regardless of whether the accessed data is resident in the data cache.
The only way to access the contents of the instruction or data cache in debug mode is by using the IC_DAT
or DC_DAT registers.
7.8.2 Instruction and Data Cache Operation with a Software Monitor
Debugger
With debug mode disabled, a software monitor debugger can use the development support registers to
assert the internal freeze signal during run-time. See
for more information.
When the internal freeze signal is asserted during run-time, the instruction cache treats all misses as if they
were from cache-inhibited regions. Misses are loaded only into the burst buffer; hits are loaded from the
cache array and the LRU bits are updated. If the debug routine is not in the instruction cache, it is loaded
from memory like any other miss and the cache state remains the same as before the freeze signal was
asserted.
For performance reasons, it may be preferable to run the debug routine from the cache. To load the debug
routine into the instruction cache before entering debug mode, perform the following procedure:
1. Save all four ways of the sets that are needed for the debug routine by reading the tag, the LRU,
valid, and lock bit states
2. Unlock the locked ways in the selected sets
3. Use the load-and-lock cache block command to load the debug routine into the instruction cache
and lock the cache blocks containing the debug routine.
4. Run the debug routine, all accesses to it will result in hits.
To restore the state of the instruction cache after the debug routine is finished, perform the following
procedure:
1. Unlock any ways in any sets that are used by the debug routine
2. Invalidate any ways in any sets that are used by the debug routine
3. Use the load-and-lock cache block command to restore the old sets in the cache array
4. Unlock any ways of the original sets that were not previously locked
5. To restore the old state of the LRU bits make sure that the last access (load-and-lock cache block
or unlock cache block command) is performed on the most-recently used way (not the LRU way).
When the internal freeze signal is asserted during run-time, the data cache treats all load misses as if they
were from cache-inhibited regions. That is, the data is loaded from memory and the cache LRU and state
bits are unchanged. Load hits are serviced from the cache array but the cache LRU and state bits are
unchanged.
When the internal freeze signal is asserted, store hits and misses are treated as write-through accesses, but
the LRU bits in the data cache array are not updated. For the dcbz instruction, data is written both into data
7-28
Section 53.4, "Software Monitor Debugger Support,"
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor