Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 433

bypass capacitors. An inductor value of 8.2 Mhz and bypass capacitor values of 0.1 µF and 10 µF provide
a two-pole filter with a cutoff frequency of 500 Hz.
VSSSYN and VSSSYN1 must have a low-impedance path to the ground plane. If sufficient isolation is
provided for VDDSYN (as described above), no additional isolation for VSSSYN and VSSSYN1 is
required.
14.5 Power Control
To optimize power consumption, the MPC885 provides a low-power mode that can be used to dynamically
activate and deactivate certain internal modules, such that only the needed modules are operating at any
given time. In addition to normal high mode (i.e. fully activated), the MPC885 supports a normal low
mode.
In addition to the normal low power-saving mode, it should be noted that the architecture of the CPM
inherently supports optimum power consumption. When the CPM is idle, it uses its own power-saving
mechanism to shut down automatically.
The normal low power mode is controlled in the PLPRCR[CSRC]. Events can cause automatic changes
from normal low to normal high mode. These events include software-initiation, CPM activity, internal
interrupt sources, external interrupt sources, and resets.
14.5.1 Normal High Mode
Normal high mode is the default mode of the MPC885. In this mode, the GCLKx frequency is determined
by SCCR[DFNH], and all modules of the MPC885 are enabled. For more information about
SCCR[DFNH], refer to Section 14.3.1.1, "Internal General System Clocks (GCLK1C, GCLK2C, GCLK1,
GCLK2)."
Normal high mode is selected if PLPRCR[CSRC]=0 and PLPRCR[LPM]=00, or if an enabled event has
caused an exit from Normal Low power mode.
14.5.2 Normal Low Mode
Normal low mode takes advantage of the low-power dividers for GCLKx to enable full functionality of
the MPC885, but at a lower frequency so that power consumption is reduced. The low-power dividers
allow the system to reduce and restore the operating frequencies of different sections of the MPC885
without losing the DPLL lock. This mode is sometimes called slow-go or low gear mode.
Normal low mode is selected if PLPRCR[CSRC]=1. In normal low mode, the GCLKx frequency is
determined by SCCR[DFNL]. For more information about SCCR[DFNL], see
General System Clocks (GCLK1C, GCLK2C, GCLK1, GCLK2)."
Normal low mode can be entered at any time, and the frequency of operation of normal low mode can be
changed dynamically. This is controlled by PLPRCR[CSRC] and SCCR[DFNL]. Changes to these bits
take effect immediately.
Freescale Semiconductor
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Clocks and Power Control
Section 14.3.1.1, "Internal
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