Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 951

0
Field
Reset
R/W
Addr
16
Field IRL
Reset
R/W
Addr
This register is affected by HRESET but is not affected by SRESET. CICR bits are described in
Bits Name
0–7 — Reserved, should be cleared.
1
8–9 SCdP SCCd priority order. Defines whether USB or SCCs asserts its request in the SCCd priority position.
00 USB asserts its request in the SCCd position.
01 SCC2 asserts its request in the SCCd position.
10 SCC3 asserts its request in the SCCd position.
11 SCC4 asserts its request in the SCCd position.
1
10–11 SCcP SCCc priority order. Defines whether USB or SCCs asserts its request in the SCCc priority position.
00 USB asserts its request in the SCCc position.
01 SCC2 asserts its request in the SCCc position.
10 SCC3 asserts its request in the SCCc position.
11 SCC4 asserts its request in the SCCc position.
1
12–13 SCbP SCCb priority order. Defines whether USB or SCCs asserts its request in the SCCb priority position.
00 USB asserts its request in the SCCb position.
01 SCC2 asserts its request in the SCCb position.
10 SCC3 asserts its request in the SCCb position.
11 SCC4 asserts its request in the SCCb position.
1
14–15 SCaP SCCa priority order. Defines whether USB or SCCs asserts its request in the SCCa priority position.
00 USB asserts its request in the SCCa position.
01 SCC2 asserts its request in the SCCa position.
10 SCC3 asserts its request in the SCCa position.
11 SCC4 asserts its request in the SCCa position.
16–18 IRL Interrupt request level. Contains the priority request level of the interrupt from the CPM that is sent
to the SIU. Level 0 indicates highest priority. IRL is initialized to zero during reset. In most systems,
value 0b100 is a good value to choose for IRL.
19–23 HP Highest priority. Specifies the 5-bit interrupt number of the CPIC interrupt source that is advanced
to the highest priority in the table. These bits can be modified dynamically. (Programming HP =
0b11111 keeps PC15 the highest priority source for external interrupts to the core.)
Freescale Semiconductor
—
0000_0000_0000_0000
18 19
HP
0000_0000_0000_0000
Figure 35-3. CPM Interrupt Configuration Register (CICR)
Table 35-3. CICR Field Descriptions
MPC885 PowerQUICC Family Reference Manual, Rev. 2
7 8 9 10 11
SCdP SCcP
R/W
0x940
23 24 25
IEN
R/W
0x942
Description
CPM Interrupt Controller
12 13 14 15
SCbP SCaP
30 31
— SPS
Table 35-3.
35-7