Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 602

Powerquicc family

Table of Contents

SDMA Channels and IDMA Emulation

storage at the end of the bus cycle. For memory reads, SAPR is automatically incremented by 1, 2,

4, or 16, depending on the address and size information specified by DCMR. See

"IDMA Parameter RAM,"

Dual-address destination write—The data in internal storage is written to the peripheral or memory

governed by the address in DAPR, the address type in DFCR, and the size in DCMR. For memory

writes, DAPR is automatically incremented by 1, 2, 4, or 16 according to DCMR. The byte count

is decremented by the number of bytes transferred. When the byte count reaches zero and the

transfer reports no errors, IDSR[DONE] is flagged, which triggers a maskable interrupt. See

Section 19.3.2, "IDMA Parameter RAM,"

Additionally, for peripheral/memory dual-address transfers, the SDACK signal asserts during the

peripheral access. For dual-address transfers, microcode performs byte-packing using a 16-byte buffer in

the dual-port RAM. Regardless of the source size, destination size, source starting address, or destination

starting address, IDMA uses the most efficient packing algorithm possible to perform the transfer in the

least number of bus cycles.

Single-Address (Single-Cycle) Transfer (Fly-By)

Each IDMA channel can be independently programmed to provide single-address, or fly-by, transfers. The

IDMA channel bypasses or flies-by internal storage since the transfer occurs directly between a device and

memory. DCMR[S/D] controls the direction of the transfer. If DCMR[S/D] = 0b01, the IDMA controller

handshakes with the peripheral for the source data and writes to the destination memory address provided.

If DCMR[S/D] = 0b10, the IDMA controller handshakes with the destination peripheral and reads from

the source memory address provided. The single-address read and write cycles are described below.

Single-address memory-read/peripheral-write—The memory address in SAPR, the address type in

SFCR, and the size in DCMR provide the data and control signals to the data bus. This bus cycle

operates like a normal read bus cycle. The SAPR is incremented by 1, 2, or 4, according to the

programming of DCMR[SIZE]. The destination device is controlled by the IDMA handshake

signals DREQ and SDACK. Asserting SDACK provides write control to the destination device.

Figure 19-10

synchronous single-address peripheral writes. See

Signals—DREQ and SDACK,"

Section 19.3.3.1, "DMA Channel Mode Registers (DCMR)."

Figure 19-11

show the transaction timing diagrams for asynchronous and

for more on IDMA handshake signals.

MPC885 PowerQUICC Family Reference Manual, Rev. 2

Section 19.3.3, "IDMA Registers."

Section 19.3.7, "IDMA Interface

Section 19.3.2,

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