Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 68

Table
Number
5-20 System Linkage Instructions ................................................................................................. 5-20
5-21 Move to/from Machine State Register Instructions .............................................................. 5-21
5-22 Move to/from Special-Purpose Register Instructions ........................................................... 5-21
6-1 Offset of First Instruction by Exception Type......................................................................... 6-2
6-2 Instruction-Related Exception Detection Order...................................................................... 6-3
6-3 Exception Priority ................................................................................................................... 6-4
6-4 Register Settings After a System Reset Interrupt Exception .................................................. 6-5
6-5 Register Settings After a Machine Check Interrupt Exception............................................... 6-5
6-6 Register Settings after an External Interrupt........................................................................... 6-7
6-7 Register Settings after an Alignment Exception ..................................................................... 6-7
6-8 Register Settings After a Program Exception ......................................................................... 6-9
6-9 Register Settings after a Decrementer Exception ................................................................. 6-10
6-10 Register Settings After a System Call Exception.................................................................. 6-11
6-11 Register Settings After a Trace Exception ............................................................................ 6-11
6-12 Register Settings after a Software Emulation Exception ...................................................... 6-12
6-13 Register Settings After an Instruction TLB Miss Exception ................................................ 6-13
6-14 Register Settings After a Data TLB Miss Exception ............................................................ 6-13
6-15 Register Settings after an Instruction TLB Error Exception................................................. 6-14
6-16 Register Settings After a Data TLB Error Exception ........................................................... 6-14
6-17 Register Settings after a Debug Exception ........................................................................... 6-15
6-18 Additional SPRs that Affect MSR Bits................................................................................. 6-17
6-19 Exception Latency................................................................................................................ 6-19
6-20 Before and After Exceptions................................................................................................. 6-19
7-1 MPC885 Family ...................................................................................................................... 7-1
7-2 Instruction Cache Control and Status Register—IC_CST ...................................................... 7-7
7-3 Instruction Cache Address Register—IC_ADR ..................................................................... 7-8
7-4 Instruction Cache Data Port Register—IC_DAT ................................................................... 7-8
7-5 IC_ADR Fields for Cache Read Commands .......................................................................... 7-8
7-6 IC_DAT Format for a Tag Read (IC_ADR[17] = 0).............................................................. 7-9
7-7 Data Cache Control and Status Register—DC_CST ............................................................ 7-12
7-8 Data Cache Address Register—DC_ADR............................................................................ 7-13
7-9 Data Cache Data Port Register—DC_DAT .......................................................................... 7-14
7-10 DC_ADR Fields for Cache Read Commands....................................................................... 7-14
7-11 DC_DAT Format for a Tag Read (DC_ADR[18] = 0)......................................................... 7-14
7-12 Copyback Buffer Select Field (DC_ADR[20–27]) Encoding .............................................. 7-15
8-1 Identical Entries Required in Level-One/Level-Two Tables .................................................. 8-9
8-2 Number of Replaced EA Bits per Page Size......................................................................... 8-11
8-3 Level-One Segment Descriptor Format ................................................................................ 8-11
8-4 Level-Two (Page) Descriptor Format ................................................................................... 8-12
8-5 Page Size Selection ............................................................................................................... 8-13
8-6 MPC885-Specific MMU SPRs ............................................................................................. 8-13
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Tables
Title
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Page
Number
Freescale Semiconductor