Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 639

clock rate. Also, if the receive and transmit sections are used to interface with the same GCI bus, set
SIMODE[CRTx] to internally connect the Rx clock and sync signals to the SI RAM transmit section. Then
define the GCI frame routing and strobe select using the SI RAM.
When the receive and transmit sections use the same clock and sync signals, the sections should use the
same configuration. Also, L1TXDx in the I/O register should be configured as an open-drain output. To
support the monitor and C/I channels in GCI, those channels should be routed to an SMC. To support the
D channel when there is no possibility of collision, clear SICR[GRx] for the SCC that supports the D
channel.
20.2.6.2.2 SCIT Mode
To interface with the GCI/SCIT bus, configure SIMODE for basic GCI/SCIT operation. Then program the
SI RAM to support a 96-bit frame length and the frame sync to be the GCI sync pulse. Generally, the SCIT
bus supports the D channel access collision mechanism. For this purpose, set SIMODE[CRTx] so the
receive and transmit sections use the same clock and sync signals and program SICR[GRx] to transfer the
D channel grant to the supporting SCC. The received bit (grant) should be marked by programming the
CSEL (channel select) bits of the SI RAM to 0b111 for an internal assertion of a strobe. This bit is sampled
by the SI and transferred to the D-channel SCC as the grant. The grant is generally bit 4 of the C/I in
channel 2 of the GCI bus, but any bit slot can be selected in the SI RAM.
20.2.6.3 GCI Interface (SCIT Mode) Programming Example
Assuming SCC2 is connected to the B1 channel, SMC2 to the B2 channel, SCC3 to the D channel, and
SMC1 to the C/I channels, the initialization sequence is as follows:
1. Program both the Rx and Tx sections of the SI RAM as shown in
entries with 0x0001_0000. Note that this example is for SCIT mode. For normal mode, delete the
last three entries in
Table 20-12. SI RAM Settings for GCI Interface (SCIT Mode)
Entry
Number
SWTR
1 0
2 0
3 0
4 0
5 0
6 0
7 0
8 0
2. SIMODE = 0x8000_80E0. Only TDMa is used. SMC1 and SMC2 are connected.
Freescale Semiconductor
Table 20-12 and set the LST bit in the new last entry.
SSEL CSEL CNT
0000 010 0000
0000 110 0000
0000 101 0000
0000 011 0001
0000 101 0101
0000 000 0110
0000 000 0001
0000 111 0000
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Table
SI RAM
BYT LST
1 0 8 bits SCC2 (B1)
1 0 8 bits SMC2 (B2)
1 0 8 bits SMC1 (M)
0 0 2 bits SCC3 (D)
0 0 6 bits SMC1 (I + A + E)
1 0 Skip 7 bytes
0 0 Skip 2 bits
0 1 D grant bit
Serial Interface
20-12. Write all unused
Description
20-33