Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 730

Powerquicc family

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SCC Asynchronous HDLC Mode and IrDA

describes reception errors.

All SCCs have 16-byte Rx FIFOs. Overrun occurs when the CP cannot keep up with the data rate

or the SDMA channel cannot write the received data to memory. The previous data byte and frame

status are lost. The controller closes the buffer and sets RxBD[OV] and SCCE[RXF]. The receiver

then looks for the next frame.

CD Lost during

The channel stops receiving frames, closes the buffer, and sets SCCE[RXF] and RxBD[CD]. This

error has highest priority. The rest of the frame is lost and other errors are not checked in that frame.

The receiver then searches for the next frame once CD is reasserted.

Abort Sequence When an abort sequence (0x7D, 0x7E for PPP; 0x7D, 0xC1 for IrLAP) is detected, the channel

closes the buffer by setting SCCE[RXF] and RxBD[AB]. CRC error status is not checked on aborted

frames. If no frame is being received, the next BD is opened and then closed with RxBD[AB] set.

The channel writes the received cyclic redundancy check to the buffer, closes the buffer, and sets

SCCE[RXF] and RxBD[CR]. After receiving this error, the receiver prepares to receive the next

Break Sequence

The receiver detected the first character in a break sequence. The channel closes the buffer and

sets SCCE[RXF] and RxBD[BRK]. CRC error status is not checked. SCCE[BRKS] is set when the

first break of a sequence is found; SCCE[BRKE] is set when an idle bit is received after a break

25.13 SCC Asynchronous HDLC Registers

The following sections describe the SCC registers when in asynchronous HDLC mode.

25.13.1 Asynchronous HDLC Event Register (SCCE)/Asynchronous HDLC

Mask Register (SCCM)

The SCC event register (SCCE) is used as the asynchronous HDLC event register to generate interrupts

and report events recognized by the asynchronous HDLC channel. When an event is recognized, the

asynchronous HDLC controller sets the corresponding SCCE bit. Interrupts can be masked by clearing the

appropriate bit in the asynchronous HDLC mask register (SCCM). SCCE bits, shown in

cleared by writing ones—writing zeros has no effect. Unmasked SCCE bits must be cleared before the

CPM clears the internal interrupt request.

0xA30 (SCCE2)/0xA34 (SCCM2) 0xA50 (SCCE3)/0xA54 (SCCM3); 0xA70 (SCCE4)/0xA74 (SCCM4)

Figure 25-4. Asynchronous HDLC Event Register (SCCE)/Asynchronous HDLC Mask Register (SCCM)

Table 25-6. Receive Errors

MPC885 PowerQUICC Family Reference Manual, Rev. 2

BRKE BRKS TXE

Freescale Semiconductor