Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 577

Powerquicc family

Table of Contents

CP Microcode Instr Addr

CP Data Addr

CP Data Addr

Shaded area is system RAM. Note that in this figure, the area is not contiguous memory. For an accurate

representation of the physical implementation, see

The dual-port RAM consists of 7 Kbytes of system RAM (see

Packages") and 1 Kbyte of parameter RAM (see

used for the following:

Storing parameters associated with the USB, SCCs, SMCs, SPI, I

Storing the BDs (in any unused dual-port RAM area)

Storing buffers (in any unused dual-port RAM area or external memory)

Storing Freescale-supplied microcode for the CP (in system RAM only)

Scratch pad area for user software (in any unused dual-port RAM area)

The dual-port RAM can be accessed either by the CP or by one of two internal U-bus masters—the

MPC8xx core or an SDMA channel. The core and the SDMA channels access the dual-port RAM in two

clocks, while the CP takes only one clock. For simultaneous accesses with at least one write operation, the

CP is delayed by one clock.

When the core or SDMA channel access the dual-port RAM, the data and address are passed through the

U-bus. The CP can fetch data from the entire dual-port RAM and microcode instructions from portions of

the system RAM.

The controller and sub-block parameters of the parameter RAM and the optional microcode packages in

system RAM use fixed addresses. The buffer descriptors, buffers, and scratch pad area, however, can be

located in any unused dual-port RAM area. See

Freescale Semiconductor

BD/Buffers/Microcode

BD/Buffers/Microcode

BD/Buffers/Microcode

BD/Buffers/Microcode

BD/Buffers/Microcode

BD/Buffers/Microcode

Parameter RAM

Figure 18-6. Dual-Port RAM Block Diagram

MPC885 PowerQUICC Family Reference Manual, Rev. 2

Section 18.7.1, "System RAM and

Section 18.7.3, "Parameter

C, and IDMAs (in parameter

Communications Processor

CP Microcode Instr

RAM") and is