Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 71

Table
Number
15-18 Address Multiplexing.......................................................................................................... 15-47
15-19 AMA/AMB Definition for DRAM Interface...................................................................... 15-48
15-20 UPMA Register Settings ..................................................................................................... 15-64
15-21 UPMB Register Settings ..................................................................................................... 15-75
16-1 PCMCIA Cycle Control Signals ........................................................................................... 16-3
16-2 PCMCIA Input Port Signals ................................................................................................. 16-4
16-3 PCMCIA Output Port Signals............................................................................................... 16-5
16-4 Other PCMCIA Signals ........................................................................................................ 16-5
16-5 Host Programming for Memory Cards ................................................................................. 16-6
16-6 Host Programming For I/O Cards ......................................................................................... 16-6
16-7 PCMCIA Registers ............................................................................................................... 16-8
16-8 PIPR Field Descriptions........................................................................................................ 16-9
16-9 PSCR Field Descriptions .................................................................................................... 16-10
16-10 PER Field Descriptions ....................................................................................................... 16-12
16-11 PGCRx Field Descriptions.................................................................................................. 16-13
16-12 PBR Field Descriptions....................................................................................................... 16-14
16-13 POR Field Descriptions ...................................................................................................... 16-15
17-1 TGCR Field Descriptions..................................................................................................... 17-8
17-2 TMR1–TMR4 Field Descriptions ......................................................................................... 17-9
17-3 TER Field Descriptions...................................................................................................... 17-11
18-1 Peripheral Prioritization ........................................................................................................ 18-3
18-2 CP Microcode Revision Number .......................................................................................... 18-4
18-3 CPM Configuration Register (CPMCFG) Bit Settings......................................................... 18-5
18-4 RCCR Field Descriptions...................................................................................................... 18-5
18-5 RMDS Field Descriptions ..................................................................................................... 18-7
18-6 CPCR Field Descriptions ...................................................................................................... 18-8
18-7 CP Command Opcodes ......................................................................................................... 18-8
18-8 CP Commands....................................................................................................................... 18-9
18-9 General BD Structure .......................................................................................................... 18-13
18-10 Parameter RAM Memory Map .......................................................................................... 18-13
2
18-11 I C and SPI Parameter RAM Relocation............................................................................ 18-14
18-12 RISC Timer Table Parameter RAM Memory Map ............................................................. 18-16
18-13 TM_CMD Field Descriptions ............................................................................................. 18-16
18-14 PWM Channel Pin Assignments......................................................................................... 18-18
19-1 U-Bus Arbitration IDs........................................................................................................... 19-3
19-2 SDCR Bit Settings ................................................................................................................ 19-5
19-3 SDSR Field Descriptions ...................................................................................................... 19-5
19-4 IDMA Parameter RAM Memory Map.................................................................................. 19-7
19-5 DCMR Field Descriptions .................................................................................................... 19-8
19-6 IDSR1/IDSR2 Field Descriptions ......................................................................................... 19-9
19-7 IDMA BD Status and Control Bits ..................................................................................... 19-11
Freescale Semiconductor
Tables
Title
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Page
Number
lxxi