Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 563

17.2.4 Timer Mode Registers (TMR1–TMR4)
The timer mode registers (TMR1–TMR4), shown in
reset the timer by clearing TGCR[RSTx].
0
Field
Reset
R/W
Addr
These registers are affected by HRESET and SRESET.
Bits Name
0–7 PS Prescaler value. The prescaler is programmed to divide the clock input by a value between 1 and 256.
A 0x00 value divides the clock by 1; 0xFF divides it by 256.
8–9 CE Capture edge and enable Interrupt
00 Disable interrupt on capture event; capture function is disabled.
01 Capture on rising TINx edge only and enable interrupt on capture event.
10 Capture on falling TINx edge only and enable interrupt on capture event.
11 Capture on any TINx edge and enable interrupt on capture event.
10 OM Output mode
0 Active-low pulse on TOUTx for one timer input clock cycle as defined by ICLK. Thus, TOUTx may
be low for one general system clock period, one general system clock/16 period, or one TINx clock
cycle period. Changes to TOUTx occur on the falling edge of the system clock.
1 Toggle TOUTx. Changes to TOUTx occur on the falling edge of the system clock.
11 ORI Output reference interrupt enable
0 Disable interrupt for reference that is reached. Does not affect an interrupt on the capture function.
1 Enable interrupt when the reference value is reached.
12 FRR Free run/restart
0 Free run. The timer count continues to increment after the reference value is reached.
1 Restart. The timer count is reset immediately after the reference value is reached.
13–14 ICLK Input clock source for the timer
00 Internally cascaded input
For TMR1, the timer 1 input is the output of timer 2.
For TMR3, the timer 3 input is the output of timer 4.
For TMR2 and TMR4, this selection means no input clock is provided to the timer.
01 Internal general system clock
10 Internal general system clock divided by 16
11 Corresponding TIN x signal (falling edge)
15 GE Gate enable.
0 TGATE x is ignored.
1 TGATE x is used to control the timer—TGATE1 for timer 1 and 2, TGATE2 for timer 3 and 4.
Freescale Semiconductor
PS
0x990 (TMR1), 0x992 (TMR2), 0x9A0 (TMR3), 0x9A2 (TMR4)
Figure 17-6. Timer Mode Registers (TMR1–TMR4)
Table 17-2. TMR1–TMR4 Field Descriptions
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Communications Processor Module and CPM Timers
Figure 17-6, are identical. Before modifying TMRx,
7 8 9 10 11
CE OM ORI
0
R/W
Table 17-2 describes the TMR fields.
Description
12 13 14 15
FRR ICLK GE
17-9