Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 494

Powerquicc family

Table of Contents

Memory Controller

Figure 15-46. Wait Mechanism Timing for an External Asynchronous Master

Handling Devices with Slow or Variable Access Times

The memory controller provides two ways to interface with slave devices that are very slow (access time

is greater than the maximum allowed by the user programming model) or cannot guarantee a predefined

access time (for example some FIFO, hierarchical bus interface, or dual-port memory devices).

These mechanisms are as follows:

The wait mechanism—Used only in accesses controlled by the UPM. MAMR[GPLA4DIS] and

MBMR[GPLB4DIS] enable this mechanism.

The external TA mechanism is used only in accesses controlled by the GPCM. ORx[SETA]

specifies whether TA is generated internally or externally.

The following sections describe how the two mechanisms work.

Hierarchical Bus Interface Example

Assume that the CPU initiates a local-bus read cycle that addresses main memory connected to the system

bus. The hierarchical bus interface accepts local bus requests and generates a read cycle on the system bus.

The programmer cannot predict when valid data can be latched by the CPU because a DMA device may

be occupying the system bus.

The wait solution (UPM)—The external module asserts UPWAIT to the memory controller to

indicate that data is not ready. The memory controller synchronized this signal because the wait

signal is asynchronous. As a result of the wait signal being asserted, the UPM enters a freeze mode

MPC885 PowerQUICC Family Reference Manual, Rev. 2

Freescale Semiconductor