Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 425

14.3.1 Clocks Derived from the DPLL Output
The MPC885 uses the following 10 internal clock signals, which are derived from the DPLL and interface
logic output clock, JDBCK:
• General system clocks—GCLK1C, GCLK2C, GCLK1, GCLK2
• Memory controller and external bus clocks—GCLK1_50, GCLK2_50
• Utopia clock — UTPCLK
• Baud rate generator clock—BRGCLK
• Synchronization clocks—SYNCCLK, SYNCCLKS
The MPC885 also provides the GCLK2_50 signal externally on the CLKOUT pin.
The DPLL and Interface output JDBCK is sent to frequency dividers that generate the GCLKx, GCLKxC,
GCLKx_50, SYNCCLK, and BRGCLK which are sent to the rest of the modules of the MPC885. The
signal, divout1, is an intermediate signal and is equivalent to JDBCK divide by 2. The division factor for
each divider is programmed in the SCCR. The organization of the dividers is shown in
divout1
DFAUTP
DFSYNC
DFBRG
Freescale Semiconductor
DFUTP
Phase
DFNH
2:1
MUX
DFNL
EBDF
Figure 14-4. Clock Dividers
MPC885 PowerQUICC Family Reference Manual, Rev. 2
UTPCLK
SYNCCLK
BRGCLK
GCLK1C
GCLK2C
GCLK2
GCLK1
GCLK1_50
Phase
GCLK2_50
Clocks and Power Control
Figure 14-4.
UTOPIA Module
CPM
CPM and
UPM
(Refresh
Timers)
Timer module,
Core, CPM and
SIU.
UPM and SIU
CLKOUT
14-9