Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 144

The MPC8xx Core
3.3 Features
Figure 3-1 shows the basic features of the MPC885.
Completion
Queue
CQ5
CQ4
CQ3
CQ2
CQ1
CQ0
One Instruction Retired
per Clock
Additional Features
• Power Dissipation Control
• Time Base Counter
• Decrementer
• JTAG
• BDM Interface
• Clock Multiplier
3-4
Sequential
Fetcher
32-Bit
Instruction
Queue
IQ3
IQ2
IQ1
IQ 0
32-Bit (One Instruction)
32-Bit
Integer
Unit
+
⁄
*
XER
ALU
Performs
EA
Calculation
Data
MMU
Entry
DTLB
Tags
U-Bus Interface
Figure 3-1. Block Diagram of the Core
MPC885 PowerQUICC Family Reference Manual, Rev. 2
32-Bit (One Instruction)
32-Bit
Branch
Processing Unit
CTR
CR
LR
INSTRUCTION UNIT
32-Bit
GPR File
(32-Entry)
L-Bus
• •
•
32-Bit
32-Bit
Kbyte
Tags
D-Cache
Load/Store
Unit (LSU)
Instruction
MMU
Entry
ITLB
Kbyte
I-Cache
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