Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 909

Table 33-9. PIP TxBD Status and Control Field Descriptions (continued)
Bits Name
2 W Wrap (last buffer descriptor in TxBD table). The number of TxBDs in the table is determined only by
the W bit and space constraints of the dual-port RAM.
0 Not the last descriptor in the TxBD table.
1 The last BD in the TxBD table. After this BD is processed, the current TxBD pointer wraps to the
top of the TxBD table (TBASE).
3 I Interrupt
0 No interrupt is generated after this buffer is serviced.
1 PIPE[TXB] is set when this buffer is serviced by the CP, which can cause an interrupt.
4 L Last
0 Not the last buffer of the frame.
1 Last buffer of the frame.
5 — Reserved and should be cleared.
6 CM Continuous mode
0 Normal operation
1 The CP does not clear R after this buffer is closed, allowing the associated buffer to be resent
when the CP next accesses this BD. However, R is cleared if an error occurs during transmission.
7–11 — Reserved, should be cleared.
12 F Fault
0 The FAULT status line has remained negated during transmission.
1 The FAULT status line has been asserted during transmission.
13 PE Paper error
0 The PERROR status line has remained negated during transmission.
1 The PERROR status line has been asserted during transmission.
14 S Select error
0 The SELECT status line has remained asserted during transmission.
1 The SELECT status line has been negated during transmission.
15 — Reserved, should be cleared.
33.5.2 The PIP Rx Buffer Descriptor (RxBD)
Using buffer descriptors, the CP confirms reception or indicates error conditions so the core knows which
buffers have been serviced.
Bit
0 1
Offset + 0 E —
Offset + 2
Offset + 4
Offset + 6
Table 33-10 describes the PIP RxBD status and control field. The data length and buffer pointer are
described in Section 33.5, "PIP Buffer Descriptors,"
Freescale Semiconductor
Figure 33-10 shows the PIP RxBD.
2 3 4 5 6
W I C — CM
Rx Buffer Pointer
Figure 33-10. PIP Rx Buffer Descriptor (RxBD)
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Description
7 8
SL
Data Length
above.
Parallel Interface Port (PIP)
15
—
33-13