Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 357

Table 12-2. MPC875/MPC870 Signal Descriptions (continued)
Hard
Name
Reset
TA Hi-Z
TEA Hi-Z
BI Hi-Z
RSV See
IRQ2 Table 12-3
KR/RETRY See
IRQ4 Table 12-3
SPKROUT
CR Hi-Z
IRQ3
1
D[0:31] Hi-Z
Freescale Semiconductor
Number Type
C12 Bidirectional Transfer Acknowledge—Indicates that the slave device addressed
active in the current transaction accepted data sent by the master (write)
pull-up or has driven the data bus with valid data (read). This is an output
when the PCMCIA interface or memory controller controls the
transaction. The only exception occurs when the memory
controller controls the slave access by means of the GPCM and
the corresponding option register is instructed to wait for an
external assertion of TA. Every slave device should negate TA
after a transaction ends and immediately three-state it to avoid
bus contention if a new transfer is initiated addressing other slave
devices. TA requires the use of an external pull-up resistor.
B12 Open-drain Transfer Error Acknowledge—Indicates that a bus error occurred
in the current transaction. The MPC875 asserts TEA when the
bus monitor does not detect a bus cycle termination within a
reasonable amount of time. Asserting TEA terminates the bus
cycle, thus ignoring the state of TA. TEA requires the use of an
external pull-up resistor.
B13 Bidirectional Burst Inhibit—Indicates that the slave device addressed in the
active current burst transaction cannot support burst transfers. It acts as
pull-up an output when the PCMCIA interface or memory controller takes
control of the transaction. BI requires the use of an external
pull-up resistor.
C9 Bidirectional Reservation—The MPC875 outputs this three-state signal with
three-state the address bus to indicate that the core initiated a transfer as a
result of a stwcx. or lwarx.
Interrupt Out 2—One of eight external inputs that can request (by
means of the internal interrupt controller) a service routine from
the core
E9 Bidirectional Kill Reservation—Input used as a part of the memory reservation
three-state protocol, when the MPC875 initiated a transaction as the result of
a stwcx. instruction.
Retry—Input used by a slave device to indicate it cannot accept
the transaction. The MPC875 must relinquish mastership and
reinitiate the transaction after winning in the bus arbitration.
Interrupt Request 4—One of eight external inputs that can request
(by means of the internal interrupt controller) a service routine
from the core.
SPKROUT—Digital audio wave form output to be driven to the
system speaker.
E10 Input Cancel Reservation—Input used as a part of the storage
reservation protocol.
Interrupt Request 3—One of eight external inputs that can
request (by means of the internal interrupt controller) a service
routine from the core.
See Bidirectional Data Bus—Bidirectional three-state bus, provides the
Figure 12-4 three-state general-purpose data path between the MPC875 and all other
devices. The 32-bit data path can be dynamically sized to support
8-, 16-, or 32-bit transfers. D0 is the msb of the data bus.
MPC885 PowerQUICC Family Reference Manual, Rev. 2
External Signals
Description
12-27