Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 434

Clocks and Power Control
The following event cause the MPC885 to leave normal low mode and enter normal high mode:
• The communications processor (CP) has a service request from a peripheral (SCC, SMC, etc.).
This option is maskable with SCCR[CRQEN].
14.6 Clock and Power Control Registers
The following sections describe the clock and power control registers.
14.6.1 System Clock and Reset Control Register (SCCR)
The DPLL has a 32-bit control register, the system clock and reset control register (SCCR), shown in
Figure 14-12, which is memory-mapped into the MPC885 SIU's register map.
0 1
Field — COM
HRESET — #
POR 0 0
R/W
Addr
16 17
Field — DFSYNC
HRESET
POR
R/W
Addr
Note: HRESET is hard reset and POR is power-on reset.
# The field is undefined
— The field is unaffected.
* PTDIV depends on the combination of MODCK1 and MODCK2. PTSEL depends on MODCK1. See
more information.
† This field is set according to the default of the hard reset configuration word.
Figure 14-12. System Clock and Reset Control Register (SCCR)
14-18
2 3 5 6
— TBS PTDIV PTSEL CRQEN
0 #
0 0
(IMMR & 0xFFFF0000) + 280
18 19 20 21
DFBRG DFNL
(IMMR & 0xFFFF0000) + 282
MPC885 PowerQUICC Family Reference Manual, Rev. 2
7 8 9 10
–
# # 0 0
* * 0 0
R/W
23 24 26
DFNH
0
0
R/W
11 12 13 14 15
— EBDF —
0 † 0
0 † 0
27 29 30 31
DFUTP DFAUTP
Table 14-5 for
Freescale Semiconductor